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所在平台: Udemy |
课程主页: https://www.udemy.com/course/xilinx-vivado-essentials-for-the-logic-designer/
课程评论：没有评论
课程名称：Xilinx Vivado基础知识为逻辑设计师 课程概述：本课程旨在帮助逻辑设计师熟悉Xilinx Vivado环境，尤其是首次为现代Xilinx设备创建设计时可能遇到的挑战。课程介绍了多种设计流程，包括仅使用HDL的设计流程、块设计流程以及HDL与块设计的混合流程。每种设计流程都包括仿真选项，并教授如何将集成逻辑分析仪（ILA）添加到设计中。此外，课程还引入了Vitis SDK，帮助逻辑设计师创建简单的测试程序，并详细说明了AXI4-Lite总线，这是处理器与逻辑之间最常用的接口。 通过本课程，学员将掌握Vivado的基础功能和工具，提升其设计能力，顺利完成现代数字逻辑设计。
Xilinx Vivado can be overwhelming for a logic designer who is creating their first design for a contemporary Xilinx device. This course describes the various design flows, including hdl only flow, block flow and a hybrid of block and hdl. Each flow includes a simulation options, and adding the Integrated Logic Analyzer to a design. We introduce the Vitis SDK to allow the logic designer to create simple test programs, and describe the AXI4-Lite bus which is the most common interface between processor and logic.
