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所在平台: Udemy |
课程主页: https://www.udemy.com/course/writing-testbenches-in-uvm-for-newbie/
课程评论：没有评论
**课程名称：** UVM Testbenches for Newbie **课程概述：** 本课程旨在为初学者介绍通用验证方法学（UVM）及其在硬件验证中的应用。随着系统复杂度的不断提升，SystemVerilog凭借其强大的功能和可重用性，已成为验证的首选语言。然而，SystemVerilog缺乏结构化的方法，而UVM则提供了一个通用的框架，极大地简化了验证平台的构建。配置数据库的引入更是革新了验证语言的使用方式。 UVM已迅速成为RTL设计验证的事实标准，并将在未来验证领域扮演重要角色。学习UVM将为VLSI从业者提供坚实的职业发展基础。 本课程是一个基于实验的课程，即使您没有面向对象编程（OOPS）或SystemVerilog的基础，也能快速上手编写UVM组件，包括：Transaction、Generator、Sequencer、Driver、Monitor、Scoreboard、Agent、Environment和Test。课程中包含大量的编程练习、项目和简单示例，以帮助您牢固掌握UVM的基础知识，并能够独立构建功能完善的UVM验证平台。 **学习目标：** * 理解UVM的核心理念和组件。 * 学习如何使用SystemVerilog和UVM库编写验证组件。 * 构建基础的UVM验证环境，包括Testbench中的各个模块。 * 掌握编写可重用、可配置验证组件的技术。 * 为进行实际的RTL设计验证打下坚实的基础。 **适合人群：** * 对VLSI设计验证感兴趣的初学者。 * 希望学习UVM以提升验证技能的设计工程师。 * 缺乏SystemVerilog或OOPS经验的新手。
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the Verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.The course will discuss the fundamentals of the Universal Verification Methodology. This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test. Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM.
