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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsdopen2020-vlsi-online-conference/
课程评论：没有评论
课程名称：VSDOpen2020 - VLSI在线会议 课程概述：加入VSDOpen2020，成为开源革命的一部分！VSDOpen2020更大更好！会议持续四天，前3天设有实时教程环节，展示了开源模拟IP的最新成果。我们兴奋地呈现过去一年研究实习生的杰出作品，并引入全新的学习和设计模拟/数字IP的技术。本次会议首次推出了一系列在开源领域取得的新项目，其中包括： 1. 由本科生和研究生从零开始使用OSU-180nm PDK、Magic和eSim EDA工具构建的开源模拟IP，令人难以置信！ 2. 向全球RISC-V社区展示如何在短短五天内从零开始使用TL-Verilog和Makerchip IDE设计基本的RISC-V内核，令人惊叹！ 3. 发布了一种基于云的VSD智能评估技术平台，使VLSI培训能够在任何时区同时进行，效果接近99%。 4. 展示如何使用真实的130nm PDK和来自efabless的OpenLANE EDA工具链开发自己的系统级芯片(SoC)。 VSDOpen2020是一个充满活力和创新的会议，鼓励学生和专业人员探索开源VLSI设计的无限可能性！
JOIN VSDOpen2020 and be a part of open-source revolution!!VSDOpen 2020 was bigger and better!!VSDOpen 2020 had LIVE Tutorial Session for first 3 daysVSDOpen 2020 showcased open-source analog IP'sVSDOpen 2020 was for 4-daysView VSDOpen2020 last day conference!!We are excited to showcase some masterpieces of work done by Research Interns over last year, and also, we are really excited to introduce you to novel techniques of learning and designing analog/digital IP's. This time, we are about to showcase you a list of projects which was achieved for the very first time in the field of open-source.To Begin with: First time in the open-source world,1. We have open-source analog IPs built from scratch using OSU-180nm PDK, Magic and eSim EDA tools, by undergrad and post-grad students. Unbelievable!!2. We displayed to the RISC-V community around the globe how you can design a basic RISC-V core in just 5-days from scratch using TL-Verilog and Makerchip IDE. Unbelievable!!3. We released a cloud-based VSD-Intelligent Assessment Technology platform which enables VLSI training for all time-zones at one go and is about 99% effective compared to any other training around the globe.4. We will show you how you can develop your own SoC using real 130nm PDK from Skywater and OpenLANE EDA tool-chain from efabless
