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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsdopen2018-first-ever-online-vlsi-conference/
课程评论：没有评论
课程名称：VSDOpen2018 - 首届在线VLSI会议 课程概述：VSDOpen2018是一项六小时的在线课程，旨在应对半导体设计中使用开源硬件工具和开发IP到达硅级的许多趋势和挑战。课程内容涵盖了一系列核心设计主题，包括IC设计与验证的前端开源EDA工具流程、数字IC的时钟树合成和优化以实现最佳性能、数字IC的面积优秀的平面布置、数字IC的最佳PPA布局与路由、标准单元布局/表征以实现紧凑区域/高性能/最小路由资源，以及机器学习在EDA中的应用。 会议的重点包括三场重要的主题演讲： - 大卫·帕特森教授的演讲《计算机架构的新黄金时代》 - 沙伦·胡教授的演讲《与ACM SIGDA的职业发展》 - 穆罕默德·卡西姆的演讲《将开放社区创新应用于硬件产品创建》 此外，还介绍了一些有关RISC-V和开源EDA的有趣论文： - 英特尔的乔治·陈宣布TAU 2019比赛 - 维也纳的菲利普·古勤展示了qflow的padframe生成器（一个开源RTL到GDS工具） - 孟买大学的阿南德·拉杰戈帕兰介绍了使用基于云的EDA工具的数字核心IC的布局与路由 - IIT马德拉斯的拉凡亚·J、安莫尔·萨霍、保罗·乔治进行的基于覆盖驱动的RISC-V核心功能验证 - 伦敦帝国学院的阿尔贝托·戈梅斯·萨伊兹展示了使用efabless平台的快速物理IC实施与集成 - 斯蒂夫·胡佛介绍了TL-Verilog - 阿科斯·哈德纳基在代尔夫特大学正式验证了WARP-V，一个开源的TL-Verilog RISC-V核心生成器 - 亚历山大大学的艾哈迈德·萨尔曼展示了使用TL-Verilog的自顶向下事务级设计 该课程为参与者提供了一个了解最新VLSI设计趋势和开源工具的机会，适合对半导体设计感兴趣的学生和专业人士。
VSDOpen2018, the six hours program, responds to many trends and challenges in semiconductor design using open source hardware tools and developing the IP to reach the silicon level, with papers and presentation in the research paper sessions covering the core set of design topics: Front-end open-source EDA tool flows for IC design and verification, Clock tree synthesis and optimization of digital IC's for best Performance, Floorplanning of digital IC's for best area, Place and Route of digital IC's for best PPA, Standard cell layout/characterization for compact area/high performance/minimal routing resources, Machine Learning in EDA.Key highlights of this conference were:Keynote by Prof. David Patterson on "A New Golden Age in Computer Architecture"Keynote by Prof. Sharon Hu on "Professional growth with ACM SIGDA"Keynote by Mohamed Kaseem on "Applying open community innovation to hardware product creation"Apart from above keynotes, here are some interesting papers, on RISC-V and opensource EDA which were presentedTAU 2019 contest announcement by George Chen from IntelPadframe generator for qflow (an opensource RTL2GDS tool) by Phillip Guhring, Vienna AustriaPNR of digital core IC using cloud based EDA tool by Anand Rajgopalan, Mumbai UniversityCoverage driven functional verification on RISC-V cores, by Lavanya J., Anmol Sahoo, Paul George from IIT MadrasRapid Physical IC implementation and integration using efabless platform by Alberto Gomez Saiz, Imperial college, LondonIntroduction to TL-Verilog by Steve Hoover, Redwood EDAFormally verifying WARP-V, an open-source TL-Verilog RISC-V Core generator by Akos Hadnagy, TU Delft Top-down transaction level design with TL-Verilog by Ahmed Salman, Alexandria University
