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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1b/
课程评论：没有评论
**课程名称：VSD - RISCV：指令集架构 (ISA) - 第二部分 (1b)** **课程概述：** 本课程是“VSD - RISCV：指令集架构 (ISA) - 第一部分 (1a)”的延续。第一部分课程涵盖了RV64I整数指令，并分析了一个RISC-V汇编语言示例程序，展示了RISC-V架构中所有32个寄存器的内容。建议学习者在开始此课程前，至少已经掌握第一部分70%的内容。 本课程将深入探讨RISC-V架构的两个关键扩展： * **乘法扩展 (RV64M)：** 学习乘法相关的指令及其应用。 * **浮点扩展 (RV64FD)：** 学习支持浮点运算的指令，这对于当今快速发展的计算领域至关重要。 此外，课程还将介绍一些与硬件相关的知识，为后续即将推出的使用Verilog语言编写RISC-V ISA的课程奠定基础。 **致谢：** 感谢SiFive公司（RISC-V ISA创建者成立的公司）以及David Patterson教授的著作《计算机组成与设计 - RISC-V版》，这些都对本课程的制作提供了巨大的帮助。 **课程内容（初步，共5个视频）：** * 重点关注RV64M（乘法扩展）的高级主题。 * 重点关注RV64FD（浮点扩展）的高级主题。 * 介绍硬件基础知识，为后续硬件实现课程做准备。
**pre-launch with 5 videos** This course is in continuation with my previous course "VSD - RISCV: Instruction Set Architecture (ISA) - Part 1a" which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture. All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course atleast 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture - An important one needed in today's fast changing computing world. We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog. So let's get started - again....Happy Learning Acknowledgements - I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA. I would also like to Thank Prof. David Patterson and his book "Computer Organization And Design - RISCV edition" which immensely helped in the making of this course. Let's get inside computers...
