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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1a/
课程评论：没有评论
课程名称：VSD - RISCV：指令集架构（ISA） - 第一部分a 概述：本课程包含5个预发布视频，重点讲解RISC-V，这是一个开放免费且自由的RISC指令集架构，最初由加州大学伯克利分校电子工程与计算机科学系开发。课程将从零开始详细讨论RISC-V ISA，并探讨计算机架构的必要性，结合真实的日常应用程序示例，展示计算机是如何运作的。课程的最终目标是帮助学员建立坚实的规格，这是系统设计的首要标准。在后续课程中，这些规格将使用RTL硬件描述语言（如Verilog/VHDL）进行编码，最终在开源EDA工具链中进行放置与布线。课程将引导学员理解规格，从有符号/无符号整数表示开始，直到RV64IMFD指令集，配以生动的图像和实例。同时，课程还将独特地探讨"IMFD"等约定，这是以往微处理器或微控制器相关课程中未曾涉及的。特别感谢SiFive公司（由RISC-V ISA的创始人成立）及大卫·帕特森教授及其著作《计算机组织与设计 - RISC-V版》，他们对课程的制作提供了极大的帮助。让我们一起深入计算机世界吧！
***pre-launched with 5 videos*** RISC-V is a free and open RISC instruction set architecture. and was originally developed in Computer Science division of the EECS Department at the University of California, Berkeley This course will talk a lot about RISC-V ISA from scratch, also including a section about why do we even need a computer architecture and how real-time day-to-day apps run on a computer, with examples The final aim of this course is to help everyone to build a robust specifications, which is the very first criteria behind system design. In the upcoming courses,, these specifications will be coded in RTL hardware description language using verilog/vhdl and finally the RTL will placed and routed using opensource EDA tool chain. This course will walk you through the specifications, starting from signed/unsigned integer representation till RV64IMFD Instruction set with some really cool images and examples. The conventions like "IMFD" will also be explored in a unique fashion, which is being never done before and any micro-processor or micro-controller related courses Acknoledgements - I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA. I would also like to Thank Prof. David Patterson and his book "Computer Organization And Design - RISCV edition" which immensely helped in the making of this course. Let's get inside computers...
