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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsd-pipelining-risc-v-with-transaction-level-verilog/
课程评论：没有评论
课程名称：VSD - 使用事务级Verilog进行RISC-V流水线设计 课程概述：您是否希望在更短的时间内构建高质量的Verilog模型？您是否已经使用Verilog实现过处理器？您实现过程中最重要的部分是什么？您的Verilog代码规模有多大？如果告诉您，通过一项新技术可以将Verilog代码规模减少约3.5倍，您会怎么想？想象一下，您可以在浏览器中以比您想象的更快的速度创建您梦想中的任何数字顺序逻辑。这将是一次“变革”。改变您过去编写Verilog代码的方式，改变您实现处理器流水线的方式。唯一不变的就是“变化”。我鼓励您与本领域的专家一同思考正确的方向，参加我于2018年2月10日举办的“使用事务级Verilog进行RISC-V流水线设计”网络研讨会，演讲者是Redwood EDA和Makerchip平台的创始人Steve Hoover。对于参加我在Udemy上RISC-V ISA课程的人来说，这个网络研讨会非常重要，因为我们将在此展示一些指令的高效RTL实现。希望您享受这个网络研讨会，祝学习愉快！
Do you want to build just verilog models or high-quality verilog models in half the time? Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser? How about a ‘change'? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only "constant". I encourage and welcome you to think in the right direction with experts from this field in my webinar on "Pipelining RISC-V with Transaction-Level Verilog" which was conducted on 10th Feb' 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform This webinar is really important for people who have taken up my RISC-V ISA course on Udemy, as we will show efficient RTL implementation of some instructions in this one. Enjoy the webinar and Happy Learning....
