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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsd-mixed-signal-risc-v-based-soc-on-fpga/
课程评论：没有评论
**课程名称：** VSD - 基于RISC-V的混合信号SoC on FPGA **课程概述：** 本在线研讨课旨在帮助您入门基础的混合信号FPGA设计流程，该流程可扩展至任何复杂的SoC设计。VSD和RedwoodEDA合作为期五天的RISC-V MTH（Microprocessors for You in Thirty Hours）工作坊，使用Makerchip平台进行事务级Verilog（TL-Verilog）编程。 对于已完成该工作坊的学员，本在线研讨课将作为第五天的延伸。在此次研讨课中，您将学习如何将以TL-Verilog编写的RISC-V流水线CPU转换为Verilog语言，并将其集成到一个混合信号SoC设计中。 **目标受众：** * **ASIC/物理设计背景的学生和工程师：** 本课程将补充您现有的知识，并深入探讨ASIC和FPGA设计流程的异同，以及在不同场景下的优势和选择理由。 * **VLSI学生、模拟设计工程师、FPGA设计师、ASIC设计师：** 本课程将连接所有这些领域的专业人士，提供一个共同的学习平台，并作为设计验证的起点。 **课程特色：** * hybridization of mixed-signal and digital design on FPGAs. * Practical application of RISC-V architecture in SoC design. * Hands-on experience with TL-Verilog and Verilog for FPGA implementation. * Insights into the comparison between ASIC and FPGA design flows. * A foundational step for design verification in complex SoCs. **未来展望：** 课程将推出后续的FPGA在线研讨会系列和为期五天的强化FPGA实操工作坊。届时将围绕OpenFPGA框架和Makerchip可视化软件进行教学，使得社区成员无需依赖物理FPGA开发板，即可学习FPGA基础知识并进行实验。 **学习目标：** * 理解混合信号SoC on FPGA的基本设计流程。 * 掌握将RISC-V CPU集成到FPGA混合信号SoC的方法。 * 了解TL-Verilog和Verilog在FPGA设计中的应用。 * 对比ASIC与FPGA设计流程的异同。 * 为进一步学习和实践FPGA设计验证打下基础。 **总而言之，本课程为对SoC设计、RISC-V架构和FPGA实现感兴趣的各领域人士提供了一个宝贵的学习机会，旨在实现“创新与共享”的学习理念。**
This webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to verilog language and is a part of a mixed-signal SoCIf you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferredThis single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verificationStay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board. Innovation at its best All the best and happy learning
