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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsd-intern-mixed-signal-physical-design-flow/
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课程名称：VSD Intern - 混合信号物理设计流程与Sky130 课程概述：本课程介绍了如何通过开源EDA工具OpenLANE进行模拟IP（如2:1模拟多路复用器）的布局与布线（PNR）设计。课程讨论了如何修改当前的IP布局，以确保其能够被EDA工具接受。混合信号系统集成电路（SoC）是同时包含模拟和数字模块的芯片。随着设计师在日常工作中逐步增加更多复杂的模拟电路，且这些电路还包含数字控制逻辑，集成的需求也在不断增长。随着工艺节点的缩小，设计师通常采取分而治之的方法，将模拟和数字结构分开处理。通常，模拟IP作为黑箱购买。 为了实现混合信号SoC的RTL到GDS流程，需要在模拟和数字模块之间建立通信。实现此集成需要在层次抽象上，决定是将模拟还是数字模块置于顶层。为此，可以利用OpenROAD项目来完成这项任务。 我们希望您享受本次课程，如有建设性反馈非常欢迎。 未来工作：包括自定义LIB以用于宏设计，并加入时序约束；对三倍高度或更高的宏进行PNR。 致谢： - Kunal Ghosh，VSD Corp. Pvt. Ltd. 联合创始人 - Openlane团队，Efabless公司 - Tim Edwards，Efabless公司模拟和设计高级副总裁 - Nickson Jose，VLSI工程师 - Prithivi Raj K，蒂鲁查拉帕利国家技术学院
This course describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, OpenLANE. It also discusses the steps to modify the current IP layouts in order to ensure its acceptance by the EDA toolsMixed signal SoC is a chip which contains both analog and digital blocks. The designers are adding more analog circuitry and increasing their complexities day by day. Not only that, they also contain digital control logic. As the process nodes shrink, the demand for integration grows. A divide and conquer approach is followed, where the analog and digital structures were dealt with separately. Usually, an analog IP (Intellectual Property) is bought as black- boxTo implement a RTL-to-GDS flow for mixed signal SoC, there is need to establish communication between the analog and digital blocks. For this integration to happen, hierarchical level of abstraction with either analog or digital as top level is required. In order to carry out this task, OpenROAD project can be utilizedHope you enjoy the session. Any constructive feedback is appreciated Future WorkTo include custom LIB for macro and include timing constraints.To perform PNR on macro of triple-height or moreAcknowledgementKunal Ghosh, Co-founder, VSD Corp. Pvt. LtdOpenlane team, Efabless corporationTim Edwards, Senior Vice President of Analog and Design at efabless corporationNickson Jose, VLSI EngineerPrithivi Raj K, National Institute of Technology Tiruchirapalli
