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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vsd-distributed-timing-analysis-within-100-lines-code/
课程评论：没有评论
课程名称：VSD - 100行代码内的分布式定时分析 课程概述：本次网络研讨会于2018年5月26日进行，探讨了在EDA时序Shell中使用`set_multi_cpu_usage`命令的影响。课程首先提出了两个关键问题：当输入`set_multi_cpu_usage -localCpu 4`和`set_multi_cpu_usage -localCpu 4 -numThreads 4`时，系统会发生什么？参与者分享了在往年前的设计公司工作时的好奇心，尤其是不同机器之间是如何启动作业的，以及在机器和作业数量失衡时，时序引擎的算法是如何处理这些问题的。 讲师Tsung-Wei Huang曾在客户现场设置分布式MMMC框架，虽然只需设置正确的变量，但对其背后的机制并不十分了解。这次学习带着好奇心展开，最终通过与Opentimer开源STA工具的架构师Tsung-Wei的交流，获得了答案。 时序分析是芯片设计流程中至关重要且复杂的任务，处理数十亿个晶体管的芯片时，时序分析的运行时间会变得非常长。此课程强调了在不同条件下（如测试模式和功能模式）进行时序分析的必要性，以及随着设计复杂度的增加，通常需要对更多的CPU和内存进行投资，而这并不经济高效。因此，引入分布式计算的方法，以加速时序收敛。 本课程将展示如何使用DTCraft这一高性能集群计算引擎，通过仅100行代码实现时序分析的分布式处理。欢迎参加“100行代码内的分布式时序分析”网络研讨会，借此机会提升自己的STA工程师或技术领导能力。 讲师简介：Tsung-Wei Huang是美国伊利诺伊大学香槟分校电气与计算机工程系的研究助理教授，拥有电气与计算机工程博士学位，并持有两项专利和超过30篇会议及期刊论文的发表。 如果你也希望找到自己的答案，欢迎报名参加即将举行的“分布式时序分析”网络研讨会，进行实践操作，理解框架，提升自身技能。
This webinar was conducted on 26th May 2018. 1) What happens when you type set_multi_cpu_usage -localCpu 4 on your EDA timing shell?2) What happens when you type set_multi_cpu_usage -localCpu 4 -numThreads 4 on your EDA timing shell? I had a curiosity, while working at my previous design companies, about how jobs are getting spawned on different machines? What if there are less machines and more jobs, and vice versa? How does the algorithm of a timing engine handles this? I myself used to setup the entire distributed MMMC framework for timing tools at customer place, which was just setting the right variables (set_multi_cpu_usage), but never knew what goes behind the tools. Its the curiosity which leads to queries which leads to exploration and finally, leads to answers. I found my answers from Tsung-Wei, who is the architect of popular opensource STA Tool Opentimer. We all know timing analysis is a really important task in overall chip design flow and its so complex and difficult task. The chip that we incorporate today has billions of transistors, resulting timing analysis runtime is tool large. Also, we need to analyze timing under different conditions, so its not just a single run that you get a final result. While there are several solutions to mitigate this computation issue, the problem is most of the work is architecturally constrained by single machine. And as design complexity continue to grow larger and larger, we have to add more and more CPU and memories to the machine, but not very cost-efficient There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That's where you need to need to distribute timing analyses across different machines.So let's distribute it and do it within 100lines of code using DTCraft - A High-performance cluster computing engine. Welcome to the webinar on "Distributed timing analysis within 100 lines of code"Do you want to find your answers too? Enroll in the upcoming webinar on "Distributed timing analysis" with Tsung-Wei, do labs on your own, understand the framework and I can guarantee you would be a better STA engineer or Lead than you were beforeSpeaker Profile:Tsung-Wei Huang Tsung-Wei Huang is Research Assistant Professor, in Department of Electrical and Computer Engineering at University of Illinois at Urbana-Champaign, IL, USA. He has done his PhD in Electrical and Computer Engineering at UIUC. He holds 2 patents and more than 30 Conference and Journal Paper publications
