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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vlsifpga-resume-project-2d-dma-controller-with-apbaxi-inf/
课程评论：没有评论
课程概览：VLSI/FPGA 简历项目：2D DMA 控制器与 APB+AXI 接口 本课程旨在教授设计一个名为 2D DMA 控制器的复杂 IP 模块，适合有志于 VLSI/FPGA 领域的学员。完成该课程后，我们将颁发为期四个月的在线实习认证。课程价格为199.99美元，前期报名者可享受高达90%的折扣。不同报名人数将对应不同的折扣比例。 在设计部分，学员将编写超过2000行的 Verilog 代码，并可通过在 zynq7010 FPGA 平台上的应用实例（如植物大战僵尸 2D 游戏）来深入理解该 IP 模块的实用性。使用这个强大的 DMA 块，学员可以创造任意的 2D 游戏，展示软件设计的能力。 该课程内容涵盖了一个具有APB3+AXI4接口的丰富功能的 2D DMA 控制器，特别设计用于图像/视频应用，同时兼容传统的 1D DMA 控制器。其主要特性包括： 1. 源/目标地址可以从任意字节位置开始（无需32位对齐）； 2. 支持二维窗口的数据复制，数据长度在每个维度为[y_size, x_size]； 3. x_size 的值范围为 [4, 65536]； 4. y_size 的值范围为 [1, 65536]； 5. 每行的 x_size 字节后可以有任意数量的字节间隔，源/目标的间隔可以不同； 6. 支持散布-收集模式（命令链表），一旦通过软件启动，最多可以复制 256 个 2D 窗口块； 7. 利用 AXI 总线协议的一些先进特性来提高数据带宽：读取命令未完成、读取数据无序、AXI 接口上的读/写并发； 对于技术问题，学员可以在讨论组中提出疑问，建议使用 Slack 应用来讨论。希望学员能在 VLSI/FPGA 设计领域找到合适的工作。
We can issue a 4-month on-line internship certification to you after the finishing of this course. Target price is $199.99 USD.1~5 enrollment: 90% discount;6~10 enrollment: 80% discount;11~20 enrollment: 70% discount;21~30 enrollment: 60% discount;31~40 enrollment: 50% discount;41~50 enrollment: 40% discount;51~99 enrollment: 30% discount;100~199 enrollment: 25% discount;Please contact (write E-mail to siliconthink@126.com or short message in Udemy) the instructor for coupon of discount.In this course, you'll design a useful and complex IP block named as 2D DMA controller. For design part, it may take about 2000+ lines of Verilog code. I will also give an application example of this IP blocks: the Plants Vs. Zombies 2D game on zynq7010 FPGA platform. Using this powerful DMA block, actually you can make any 2D games. This's just effort of software.If you follow me to finish this project, it must be a big plus that can make your stand out from other candidates. And you can learn to design other complex IP blocks.It' a rich feature 2D DMA controller with APB3+AXI4 interface. It's specially designed for image/video application, while compatible with traditional 1D DMA controller. Here are the main features (should be competitive with DMA IP from ARM or Synopsys):1) source/destination address can start from any byte location (no need 32bit aligned);2) Support data copy of 2D window with data length in each dimension is [y_size, x_size];3) Value range for x_size is [4, 65536];4) Value range for y_size is [1, 65536];5) There can be any number of byte gap after each line of x_size byte; And the gap for source/destination can be different;6) Support scatter-gather mode (command linked list); Once started by SW, it can copy at most 256 blocks of 2D window;7) Utilize some advanced feature to AXI bus protocol to improve data bandwidth: read cmd outstanding, read date out-of-order, concurrency of read/write on AXI interface;Any Tech. problem, you can drop your question in a discussion group, using slack APP. Please check the introduction section for detailed Info. about technic support.Wish you can find a decent job in VLSI/FPGA design.
