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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vlsi-academy-sta-checks/
课程评论：没有评论
**课程名称：** VSD - 静态时序分析 - I **课程概述：** 本课程是静态时序分析（STA）系列的第一部分，专注于**关键的时序检查**。STA 涉及时序检查、约束和库，为避免内容过于庞杂，本系列课程分为三个部分。本课程将帮助您宏观了解当前行业在芯片签核（sign-off）阶段所进行的各种时序检查，并为您介绍理解更高级 STA 课程所需的**基本时序术语**。 尽管时序分析贯穿物理设计的整个流程，但本课程主要聚焦于**签核时序**，即深入检查设计的每一个角落，识别任何潜在的时序违规。课程从基础概念讲起，以中等进度逐步深入，最终达到中级水平，确保您能全面掌握相关细节。 **学习目标：** * 掌握 STA 中的核心时序检查项。 * 理解在芯片签核中进行时序分析的重要性。 * 熟悉 STA 所需的基础时序术语。 * 识别和理解潜在的时序违规。 **目标学员：** * 对物理设计和芯片设计感兴趣的学生或工程师。 * 希望深入了解静态时序分析原理和实践的人员。 **学习体验：** 本课程设计由浅入深，逐步引导学习者掌握 STA 的关键知识，旨在提供一个全面而易于理解的学习体验。
Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA. Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details Hope you enjoy learning this course in the same way we enjoyed making them. Happy Learning!!
