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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis-part2/
课程评论：没有评论
**课程名称：** VSD - 时钟树综合 - 第二部分 **课程概述：** 本课程是 "VLSI Academy - 时钟树综合 - 第一部分" 的后续课程，强烈建议先学习第一部分。时钟是任何VLSI芯片的关键组成部分。本课程将带您进入从零开始为数百万触发器构建时钟树的高级阶段。虽然我们将很快推出一些实验性视频和课程，但作为补充，本课程包含真实芯片中遇到的实时示例和问题，以及相应的解决方案。 **课程结构：** 1. **引言** 2. **时钟树优化检查清单** 3. **如何为不均匀分布的时钟端点构建时钟树** 4. **功耗感知时钟树综合** 5. **带真实时钟的时序静态分析** **学习体验：** 这门课程提供了在真实芯片设计中遇到的实际问题和解决方案，相信您将获得前所未有的学习体验。期待在课堂上与您相见！
This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop. While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even solutions to those problems The course is structured in below format: 1) Introduction 2) Clock tree optimization checklist 3) How to build clock tree for uneven spread of clock end-points 4) Power aware clock tree synthesis 5) Static timing analysis with real clocks Sounds interesting!! Right!! So get in and have the greatest learning experience like you had never before See you in class!!
