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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vlsi-academy-circuit-design/
课程评论：没有评论
这门 Coursera 课程“VSD - 电路设计与 SPICE 仿真 - 第一部分”面向 VLSI 专业人士和对时序分析有一定了解的学生。课程旨在深入探讨静态时序分析（STA）的根本问题，例如： * 单元延迟的真正来源是什么？ * 延迟模型的准确性如何？ * 如何验证 STA 的结果是否正确？ 课程将通过 SPICE（Simulation Program for Integrated Circuit Emphasis）仿真来提供这些问题的答案，并鼓励学员进行实践操作。这是一门为认真进行时序分析的专业人士量身定制的课程。
So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis. OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk, But, sit back, and give it a thought "Have you done it all?" "Did you know, where does the delay of a cell actually comes from?" "We have learnt about delay models, but are the models accurate?" "How do you verify, if what you are doing in static timing analysis, is correct?" and many more. These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own. And, here's the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst So let's get started and keep those questions coming in the forum, and I will answer all of them. See you in class!!
