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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vhdl-fpga-engineer-with-xilinx-vivado-design-suite/
课程评论：没有评论
课程名称：使用Vivado设计套件的FPGA工程师VHDL课程 课程概述： FPGA的应用日益广泛，涉及多个领域，需求持续增长。本课程专注于VHDL语言，这是两种最流行的硬件描述语言之一（另一种为Verilog），各自具有独特的优势。一旦掌握其中一种语言，就能更容易理解另一种，从而结合两者的能力构建复杂系统。课程内容根据大多数相关公司的需求技能进行设计，旨在帮助学员通过实际案例理解关键概念。 课程内容详细讲解了以下主题： - 模型风格的使用 - 阻塞和非阻塞赋值 - 可综合的有限状态机（FSM） - 基于块和分布式内存资源的内存构建 - Vivado IP集成器 - 硬件调试技术，例如ILA和VIO 此外，课程探讨了FPGA设计流程，使用Xilinx Vivado设计套件并讨论实现策略以获得理想性能。通过多个详细项目，学员将理解如何利用Verilog构造与真实外设设备进行接口的技术。课程中还包含独立章节，讲解如何编写测试平台和FPGA架构，加深对FPGA内部资源的理解及设计验证步骤。 总体而言，本课程为FPGA工程师提供了全面的VHDL语言学习和实战经验，帮助学员在这一不断发展的领域中增强能力。
FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic. The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.
