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所在平台: Udemy |
课程主页: https://www.udemy.com/course/vhdl-design-and-modeling-of-digital-systems/
课程评论：没有评论
课程名称：利用Xilinx Zynq-7000 ARM/FPGA SoC学习VHDL设计 课程概述：本课程旨在教授学员如何利用VHDL分析和合成数字系统，以设计和仿真FPGA、ASIC和VLSI数字系统。参与者将学习VHDL的基本概念和实用设计技术，使用Xilinx FPGA开发板和仿真软件进行实践经验的积累。课程重点包括VHDL方法论和逻辑合成设计流程，涵盖与组件建模、数据流描述和硬件行为描述相关的设计问题。学员将重点理解硬件描述语言VHDL，学习逻辑合成的设计技术、设计标准及VHDL应用。 学习目标：课程结束后，参与者将能够： 1. 描述并解释VHDL的语法和语义； 2. 使用VHDL创建可合成的设计； 3. 使用Digilent Zybo Z7 Zynq-7000 ARM/FPGA SoC开发板进行实际操作； 4. 使用Xilinx Vivado工具集； 5. 在VHDL中设计简单实用的测试平台； 6. 设计和开发VHDL模型。 先决条件：学员需熟悉数字逻辑设计、电气工程或具有等同经验。即使您已经对VHDL有所了解，若您从未使用过‘event’以外的属性、从未使用过变量、总是使用无法简化为单一并发语句的流程、总是在测试平台中使用assert或report语句、从未使用无约束的向量或数组、从未在实体内使用过被动流程、从未在可合成代码中使用过实数或math_real库、始终对每个信号分配使用单个过程等，那么本课程对您来说同样具有重要意义。您将学习有限状态机设计、双流程设计方法、测试平台设计、组合和时序逻辑以及可扩展的可合成设计。
Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA, ASIC, and VLSI digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications. At the end of this course, participants will be able to accomplish the following: Describe and explain VHDL syntax and semanticsCreate synthesizable designs using VHDLUse Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board for hand-on experienceUse the Xilinx Vivado toolsetDesign simple and practical test-benches in VHDLDesign and develop VHDL models Prerequisites: Familiarity with digital logic design, electrical engineering, or equivalent experience. Even if you're now already familiar with VHDL but you've: Never used an attribute other than ‘event?Never used variables?Always used a process where a single concurrent statement would have sufficed?Never used assert or report statements except (maybe) in a test-bench?Never used an unconstrained vector or array?Never used a passive process inside of an entity?Never used a real or the math_real library package in synthesizable code?Always used a single process per signal assignment? then this course will definitely have something for you as well. You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable.
