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所在平台: Udemy |
课程主页: https://www.udemy.com/course/verilog-for-an-engineer-with-xilinx-vivado-design-suite/
课程评论：没有评论
课程名称：使用Xilinx Vivado设计套件的FPGA工程师Verilog课程 课程概述：FPGA（现场可编程门阵列）在各个领域中的应用不断增加，为其设计与开发创造了更多的机会。本课程专注于Verilog语言，它是两种最流行的硬件描述语言之一（另一种是VHDL），两者各具优势。掌握其中一种语言后，学习另一种将变得简单，从而可以利用两者的特性构建复杂系统。 本课程根据行业中企业对FPGA工程师的技能需求设计，内容通过实践案例进行讲解，以帮助学员理解和构建逻辑。课程涵盖以下主题：建模风格、阻塞与非阻塞赋值、可综合的有限状态机（FSM）、利用块内存和分布式内存资源构建内存、Vivado IP集成器，以及硬件调试技术（如ILA和VIO）。 课程深入探讨了使用Xilinx Vivado设计套件的FPGA设计流程，同时讨论了实现策略以达到所需的性能。通过多个项目实例，学员将了解如何使用Verilog语言接口与FPGA的实际外部设备。此外，课程还专门设置了编写测试平台（Testbench）和FPGA架构的部分，进一步加深对FPGA内部资源的理解及设计验证的步骤。 此课程旨在帮助学员掌握Verilog语言，熟悉FPGA开发流程，从而为FPGA工程师的职业生涯奠定坚实的基础。
FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the Verilog language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic. The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.
