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所在平台: Udemy |
课程主页: https://www.udemy.com/course/uvm-for-verification-part-3register-abstraction-layer-ral/
课程评论：没有评论
**Coursera课程总结：UVM RAL入门** 本课程是“Verification Series”的第五部分，专注于UVM寄存器抽象层（RAL）的基础知识。 **课程概述：** 随着系统复杂性的不断提升，SystemVerilog凭借其强大的功能和可重用性，已成为验证的首选语言。而UVM（Universal Verification Methodology）则提供了一个标准化的框架，帮助验证工程师构建结构化的测试平台。在本课程中，我们将重点介绍UVM的配置数据库（configuration database）如何改变传统的验证方法。 UVM已成为RTL验证的事实标准，掌握UVM对于VLSI领域的职业发展至关重要。课程将详细讲解UVM寄存器层（UVM Register layer）提供的库，这些库能够简化包含寄存器和存储器的DUT（Design Under Test）的验证。UVM RAL通过一套抽象方法，支持前门（front-door）和后门（back-door）两种访问机制，这些机制不仅易于使用，而且高度可配置。此外，课程还将涵盖如何利用UVM RAL进行覆盖率（coverage）的计算。 **学习要点：** * 理解SystemVerilog在现代验证中的作用。 * 掌握UVM作为标准化验证方法的重要性。 * 学习UVM配置数据库（configuration database）的应用。 * 深入了解UVM寄存器抽象层（UVM RAL）及其提供的库。 * 掌握UVM RAL的前门和后门访问机制。 * 学习使用UVM RAL进行覆盖率的计算。
Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.The UVM Register layer provides a set of libraries for adopting UVM for verification of DUTs consisting of registers as well as memories. UVM RAL provides a set of abstract methods to access the register as well as memories with either a front-door or back-door access mechanism that are easy to use as well as configurable. We will also be covering the coverage computation we get with UVM RAL.
