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所在平台: Udemy |
课程主页: https://www.udemy.com/course/uvm-for-verification-part-2-projects/
课程评论：没有评论
**课程名称：** 验证系列第四部分：UVM 项目 **课程概述：** 本课程是继 RTL 设计完成之后，关于 Verilog 测试平台开发的实践性课程。在系统复杂性日益增长的今天，SystemVerilog 以其强大的功能和可重用性成为验证的首选语言，能帮助验证工程师快速定位隐藏的 Bug。然而，SystemVerilog 在结构化方法上仍有不足，而 UVM (Universal Verification Methodology) 正是为此设计，提供了一个通用的验证框架。 UVM 的引入，特别是配置数据库 (configuration database) 的应用，彻底改变了以往的验证工作方式。在短短几年内，验证工程师们已广泛认识到 UVM 的强大能力，并将其采纳为 RTL 设计验证的事实标准。鉴于 UVM 在验证领域的长期发展前景，学习 UVM 将为 VLSI 从業者提供宝贵的职业发展机会。 本课程为实验课程，重点在于展示验证工程师如何运用 UVM 对 FPGA 中常见的 RTL 和子模块进行验证。课程内容涵盖： * **组合逻辑验证：** 如加法器。 * **时序逻辑验证：** 如 D 触发器。 * **通信接口验证：** 如时钟发生器、UART、SPI 和 I2C。 * **总线协议验证：** 如 APB、AXI。 * **UVM 核心概念演示：** 包括虚拟序列器 (virtual sequencer)、TLM 分析 FIFO (TLM analysis FIFO) 和序列库 (sequence library)。 本课程适合已掌握 UVM 基础知识的学习者，通过实际项目案例，帮助理解 UVM 在实际验证工作中的应用。
Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.This is a Lab-based course designed such that anyone with the fundamentals of UVM could understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGA. The course covers verification of the combinational circuit like combinational adder, Sequential circuit like Data flip-flop, communication interfaces like a clock generator, UART, SPI, and I2C, and Bus protocols like APB, AXI, and demonstration of few useful UVM concepts like a virtual sequencer, TLM analysis FIFO, and a sequence library.
