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所在平台: Udemy |
课程主页: https://www.udemy.com/course/uvm-for-verification-part-1-fundamentals/
课程评论：没有评论
**课程名称：** Verification Series Part 3: UVM Essentials **课程概述：** 本课程是关于Universal Verification Methodology (UVM) 基础的实践性课程。在完成RTL设计后，编写Verilog测试平台是确保设计在测试场景下无误的重要环节。随着系统复杂性的不断增长，SystemVerilog以其强大的功能和可重用性成为验证的首选语言，帮助验证工程师快速定位隐藏的bug。尽管SystemVerilog缺乏结构化方法，UVM却致力于提供一个通用的框架。配置数据库的引入改变了以往的验证语言工作方式。在短短几年内，UVM的强大能力已被验证工程师广泛认可，并成为RTL设计验证的行业标准。UVM在验证领域将有长远的发展，学习UVM对VLSI从业者在该领域发展职业生涯大有裨益。 本课程将深入探讨UVM的基础知识。这是一门基于实验的课程，即使没有任何面向对象编程（OOPS）或SystemVerilog经验的学习者，也能立即开始编写UVM组件，包括：Transaction, Generator, Sequencer, Driver, Monitor, Scoreboard, Agent, Environment, Test。课程中将通过大量的编码练习、项目和简单示例，帮助学员建立扎实的UVM基础。
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the Verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.The course will discuss the fundamentals of the Universal Verification Methodology. This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test. Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM.
