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所在平台: Udemy |
课程主页: https://www.udemy.com/course/systemverilog-testbenches-for-newbie-with-xilinx-vivado-2020/
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课程名称：使用Xilinx Vivado 2020学习SystemVerilog测试平台 课程概述：VLSI行业主要分为两个流行领域：系统设计与系统验证。在这个领域，Verilog和VHDL仍然是大多数设计工程师的热门选择。尽管初步的功能验证可以通过硬件描述语言（HDL）进行，但HDL在执行代码覆盖分析、极端情况测试等方面的能力有限，有时甚至无法进行这些检查。因此，像SystemVerilog这样的专门验证语言逐渐成为设计验证的主要选择。SystemVerilog的面向对象特性允许使用继承、多态等功能，从而增加了发现设计中关键错误的能力，而这些错误HDL无法检测。与设计数字系统相比，验证过程无疑更为复杂和有趣，因此包含大量的面向对象编程（OOP）构造。SystemVerilog已成为数字系统验证工程师的热门选择。该课程将引导你学习编写SystemVerilog测试平台和进行芯片验证的常见技术。课程结构设计合理，任何希望学习SystemVerilog的人都能理解内容。最后，实践是成为专家的关键。
VLSI Industry is divided into two popular branches viz. Design of System and Verification of the System. Verilog, VHDL remain the popular choices for most Design Engineers working in this domain. Although, preliminary functional verification can be carried out with Hardware Description Language. Hardware Description language possesses limited capabilities to perform code coverage analysis, Corner cases testing, etc and in fact sometimes it becomes impossible to perform this check with HDL's. Hence Specialized Verification languages such as SystemVerilog start to become the primary choice for the verification of the design. The SystemVerilog Object-oriented nature allows features such as Inheritance, Polymorphism, etc. adds capabilities of finding critical bugs inside design that HDL simply cannot find. Verification is certainly more tricky and interesting as compared to designing a digital system and hence it consists of a large number of OOP's Constructs as opposed to Verilog. SystemVerilog is one of the most popular choices among Verification Engineer for Digital System Verification. This Journey will take you to the most common techniques used to write SystemVerilog Testbench and perform Verification of the Chips. The course is structured so that anyone who wishes to learn about System Verilog will able to understand everything. Finally, Practice is the key to become an expert.
