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所在平台: Udemy |
课程主页: https://www.udemy.com/course/systemverilog-functional-coverage-for-newbie/
课程评论：没有评论
课程名称：验证系列第七部分：SystemVerilog功能覆盖 课程概述：随着硬件描述语言（HDL）和知识产权（IP）的发展，验证过程变得越来越复杂且耗时。HDL增加了使工程师能够设计并编写复杂系统测试平台的能力，但验证设计意图和决定合适的刺激集以满足验证计划并不总是容易。因此，SystemVerilog通过引入断言和覆盖来满足这一需求，为语言添加了独立的构造。SystemVerilog的断言使我们能够在时间和非时间域中验证设计者的意图。功能覆盖则像是我们向设计单元（DUT）发送刺激的反馈，帮助我们以最短的时间找到验证计划的最佳刺激。 本课程涵盖不同类型的覆盖桶（bins）的基础知识，包括隐式桶、显式桶、通配符桶、忽略桶、默认桶和非法桶，并为每种桶提供RTL示例。课程详细讨论了覆盖组（Cover group）、可重用覆盖组（Reusable Covergroup）和不同的采样方法，包括事件、sample()方法和用户定义的采样方法。此外，功能覆盖使我们能够通过交叉覆盖验证信号之间的关系，课程中详细讨论了交叉覆盖及其不同组合过滤策略。最后，过渡桶（Transition bins）赋予功能覆盖时间特性，课程中也详细讨论了功能覆盖在Verilog和SystemVerilog测试平台中的使用示例。
The verification process is becoming complex and time-consuming day by day with advances in the Hardware Description Languages and IPs. HDL has added capabilities that allow the engineer to Design and write Testbench for complex systems. But verifying designer intent and deciding set of right stimuli to meet the Verification plan is not always easy with HDL. Hence System Verilog introduces assertions and Coverage to fulfill this requirement by adding independent constructs to language. SystemVerilog assertions allow us to verify Designer intent in both Temporal and Non-Temporal domains. Functional Coverage act like feedback for the stimulus we are sending to DUT so that we could reach to best stimulus for verifying the plan in the least amount of time. This course covers the fundamentals of different types of bins viz, Implicit bins, Explicit bins, Wildcard bins, Ignore bins, default bins, illegal bins with a demonstration of each of them in RTL. Fundamentals of Cover group, Reusable Covergroup, and different Sampling methods viz. event, sample() method, and User-defined Sample Method are discussed in detail. Functional Coverage gives us the ability to verify the relation between the signal by using Cross Coverage and detailed discussion on Cross coverage with different combination filtering strategies are covered in detail. Finally, Transition bins provide temporal abilities to Functional Coverage is also discussed in detail with projects demonstrating the usage of Functional Coverage in Verilog and SystemVerilog Testbench.
