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所在平台: Udemy |
课程主页: https://www.udemy.com/course/systemverilog-functional-coverage/
课程评论：没有评论
课程名称：SystemVerilog功能覆盖语言入门 课程概述：本课程旨在帮助学员掌握系统中的关键设计漏洞，尤其是那些难以发现的设计缺陷。SystemVerilog功能覆盖语言及其方法论是整体功能验证方法中一个非常重要的部分，所有验证工程师都需要掌握这一知识，以获得成功。掌握功能覆盖（FC）知识将成为求职或参与项目时简历上的亮点。课程提供了逐步学习FC的指导，并结合实际应用，帮助学员巩固概念，并在最短时间内将FC应用于实际项目中。FC帮助实现功能和时间域的关键覆盖，这是代码覆盖无法做到的。本课程不要求学员具备SystemVerilog、面向对象编程或UVM的先前知识。课程共计9节讲座，将带领您从零开始逐步学习功能覆盖语言。
The knowledge gained from this course will help you cover those critical and hard to find design bugs. SystemVerilog Functional Coverage Language and Methodology is a very important part of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of FC will indeed be a highlight of your resume when seeking a challenging job or project The course offers step-by-step guide to learning of FC with real life applications to help you solidify your concepts and apply FC to your project in shortest possible time. FC helps the critical part of Functional/Temporal domain coverage which is simply not possible with code coverage.The course does not require any prior knowledge of SystemVerilog or OOP (Object oriented programming) or UVM. The course has 9 lectures that will take you step by step through FC language from scratch.
