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所在平台: Udemy |
课程主页: https://www.udemy.com/course/systemverilog-for-verification-part-2-projects/
课程评论：没有评论
课程名称：验证系列第二部分：系统Verilog项目实践 概述：VLSI行业可分为两个分支，即RTL设计和RTL验证。Verilog和VHDL仍然是大多数RTL设计工程师的热门选择。功能验证虽也可使用硬件描述语言进行，但硬件描述语言在代码覆盖分析、边缘情况测试等方面的能力有限，而对于复杂系统的TB代码编写有时变得几乎不可能。SystemVerilog已经成为验证工程师验证复杂RTL的主要工具。SystemVerilog的面向对象能力（如继承、多态和随机化）使用户能够以最小的努力发现关键bug。FPGA中的每个复杂系统都是通过多个子系统构建而成，这些子系统可以是简单的顺序组件、简单的组合组件、数据通信协议RTL或总线协议RTL。一旦我们理解了对常见子系统进行验证的策略，就可以轻松地用相同的逻辑来验证任何复杂系统。课程的目标是基于第一部分课程中讨论的基础知识，构建逻辑以验证这些常见子系统。我们将从对数据触发器和FIFO的验证开始，然后进行对常见数据通信协议（如SPI、UART和I2C）的验证，最后验证总线协议（如ABP、AHB、AXI和Wishbone协议）。
The VLSI industry can be divided into two branches, viz., design of RTL and verification of the RTL. Verilog and VHDL remain the popular choices for most design engineers working in RTL design. Functional verification could also be performed with the Hardware Description Language, but the Hardware Description Language has limited capabilities for performing code coverage analysis, corner case testing, and so on, and writing TB code may be impossible for complex systems at times.SystemVerilog has become the primary choice of verification engineers to perform verification of complex RTL's. SystemVerilog object-oriented capabilities such as inheritance, polymorphism, and randomization allow users to find critical bugs with minimum effort. Each complex system in FPGAs is built with the help of multiple subsystems. These subsystems can be either simple sequential components / simple combinational components / data communication protocols RTL / bus protocol RTL. Once we understand strategies to perform verification of the common subsystems, you can easily perform verification of any complex system with the same logic. Our objective for the course will be to build logic with the help of the fundamentals discussed in the first part of the course to perform verification of these common subsystems. We start our course by performing verification of data flipflops and FIFOs, then proceed to verification of common data communication protocols, viz., SPI, UART, and I2C. Finally, we will perform the verification of bus protocols, viz., ABP, AHB, AXI, and Whishbone protocol.
