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所在平台: Udemy |
课程主页: https://www.udemy.com/course/systemverilog-assertions-sva-with-xilinx-vivado-20201/
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课程名称：SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1 课程概述： 该课程旨在介绍如何将SystemVerilog Assertions (SVA) 应用于Xilinx Vivado 2020.1开发环境中，以有效验证RTL设计。课程强调了在设计验证中引入断言的重要性，无论底层硬件验证语言 (HVL) 是Verilog、SystemVerilog还是UVM，断言都能帮助快速定位bug。与基于Verilog的行为检查相比，SVA在实现复杂时序序列方面具有更简洁的语法，能显著节省时间和精力。 课程内容将涵盖： * SVA的基础知识和核心构造。 * SVA在Vivado中的原生支持情况以及 Vivado尚不支持的SVA实现的替代方案。 * SVA的三种主要类型：即时断言 (Immediate Assertion)、延迟即时断言 (Deferred Immediate Assertion) 和最终延迟即时断言 (Final deferred immediate assertion)，以及并发断言 (Concurrent Assertion)。 * 即时/延迟断言用于非时序域的功能验证。 * 并发断言用于时序域的验证。 * 通过大量示例，帮助学习者建立选择正确断言策略以验证RTL行为的基础，以及如何在实践中运用SVA。 * 培养选择和运用SVA操作符以满足设计规范的经验。
Welcome to Nowadays, Incorporating the Assertions in the Verification of the design is common to verify RTL behavior against the design specification. Independent of the Hardware Verification Language( HVL ) viz. Verilog, SystemVerilog, UVM used for performing verification of the RTL, the addition of the assertions inside the Verification code helps to quickly trace bugs. The primary advantage of using SV assertion over Verilog-based behavior check is a simplistic implementation of the complex sequence that can consume a good amount of time and effort in Verilog-based codes. SystemVerilog assertion has a limited set of operators so learning them is not difficult but choosing a specific operator to meet design specifications comes with years of experience. In this course, We will go through series of examples to build a foundation on choosing a correct assertion strategy to verify the RTL Behavior. The assertion comes in three flavors viz. Immediate Assertion, Deferred Immediate assertion, Final deferred immediate assertion, and Concurrent Assertion. An assertion is a code responsible for verifying the behavior of the design. Full Verification of the design essentially includes verification in Temporal as well as non-temporal domains. SV Immediate and Deferred assertions allow us to verify the functionality of the design in the Non-Temporal region and Concurrent assertion allows us to verify the design in the Temporal region. Welcome to the Fascinating World of SV assertions. The course will discuss the Fundamentals of SV assertion constructs that Vivado natively supports and alternative ways of implementing constructs that Vivado doesn't support yet.
