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所在平台: Udemy |
课程主页: https://www.udemy.com/course/systemverilog-assertions-for-newbie/
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Coursera 课程《Verification Series Part 6: SystemVerilog Assertions Basics》主要介绍了在 RTL 验证中引入断言（Assertions）的重要性及其基本概念。 **核心内容：** * **断言的优势：** 强调了在验证代码中加入断言，无论使用何种硬件验证语言（HVL），如 Verilog、SystemVerilog 或 UVM，都能帮助快速定位 bug。相较于 Verilog，SystemVerilog 断言在实现复杂时序检查方面更加简洁高效。 * **SystemVerilog 断言基础：** 解释了 SystemVerilog 断言运算符数量有限，易于学习，但选择合适的运算符以满足设计规范则需要经验积累。 * **断言策略：** 通过一系列示例，课程旨在帮助学员建立选择正确断言策略以验证 RTL 行为的基础。 * **断言的种类：** 介绍了三种主要类型的断言：立即断言（Immediate Assertion）、延迟立即断言（Deferred Immediate Assertion）、最终延迟立即断言（Final deferred immediate assertion）和并发断言（Concurrent Assertion）。 * **断言的作用域：** 阐述了立即断言和延迟立即断言用于验证设计的非时序（Non-Temporal）行为，而并发断言则用于验证设计的时序（Temporal）行为。 总而言之，本课程为学习者提供了 SystemVerilog 断言的基本知识，以及如何利用它们来有效地验证 RTL 设计的行为。
Nowadays, Incorporating the Assertions in the Verification of the design is common to verify RTL behavior against the design specification. Independent of the Hardware Verification Language( HVL ) viz. Verilog, SystemVerilog, UVM used for performing verification of the RTL, the addition of the assertions inside the Verification code helps to quickly trace bugs. The primary advantage of using SV assertion over Verilog-based behavior check is a simplistic implementation of the complex sequence that can consume a good amount of time and effort in Verilog-based codes. SystemVerilog assertion has a limited set of operators so learning them is not difficult but choosing a specific operator to meet design specifications comes with years of experience. In this course, We will go through series of examples to build a foundation on choosing a correct assertion strategy to verify the RTL Behavior. The assertion comes in three flavors viz. Immediate Assertion, Deferred Immediate assertion, Final deferred immediate assertion, and Concurrent Assertion. An assertion is a code responsible for verifying the behavior of the design. Full Verification of the design essentially includes verification in Temporal as well as non-temporal domains. SV Immediate and Deferred assertions allow us to verify the functionality of the design in the Non-Temporal region and Concurrent assertion allows us to verify the design in the Temporal region.
