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所在平台: Udemy |
课程主页: https://www.udemy.com/course/system-verilog-for-chip-verification/
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课程名称：为初学者编写SystemVerilog测试平台 课程概述：本课程专注于VLSI行业中的两个主要分支：系统设计和系统验证。尽管大多数设计工程师仍然选择使用Verilog和VHDL进行初步的功能验证，但硬件描述语言在执行代码覆盖分析和边角案例测试方面存在一定的局限性，有时甚至无法进行这些检查。因此，专门的验证语言SystemVerilog逐渐成为设计验证的主要选择。SystemVerilog的面向对象特性（如继承、多态等）增强了其在发现设计中关键缺陷方面的能力，这是HDL无法实现的。相比数字系统设计，验证工作更为复杂且富有挑战性，涉及大量的面向对象编程（OOP）构造。 本课程将带领学员了解编写SystemVerilog测试平台和进行芯片验证的常用技术。课程内容经过精心结构设计，使任何希望学习SystemVerilog的人都能够理解相关知识。最后，实践是成为专家的关键。
VLSI Industry is divided into two popular branches viz. Design of System and Verification of the System. Verilog, VHDL remain the popular choices for most Design Engineers working in this domain. Although, preliminary functional verification can be carried out with Hardware Description Language. Hardware Description language possesses limited capabilities to perform code coverage analysis, Corner cases testing, etc and in fact sometimes it becomes impossible to perform this check with HDL's. Hence Specialized Verification languages such as SystemVerilog start to become the primary choice for the verification of the design. The SystemVerilog Object-oriented nature allows features such as Inheritance, Polymorphism, etc. adds capabilities of finding critical bugs inside design that HDL simply cannot find. Verification is certainly more tricky and interesting as compared to designing a digital system and hence it consists of a large number of OOP's Constructs as opposed to Verilog. SystemVerilog is one of the most popular choices among Verification Engineer for Digital System Verification. This Journey will take you to the most common techniques used to write SystemVerilog Testbench and perform Verification of the Chips. The course is structured so that anyone who wishes to learn about System Verilog will able to understand everything. Finally, Practice is the key to become an expert.
