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所在平台: Udemy |
课程主页: https://www.udemy.com/course/synthesizable-vhdl-programming-and-fpgas/
课程评论：没有评论
**课程名称：**VHDL电路设计与FPGA (使用Vivado与Modelsim) **课程概述：** 本课程旨在教授VHDL电路设计，从基础概念入手，并通过FPGA开发板的实际应用进行讲解。课程将涵盖组合逻辑和时序逻辑电路设计，并提供具体示例。学员将学习使用Vivado或Modelsim平台进行VHDL设计的仿真与开发。部分代码将烧录至FPGA板进行演示。 **核心内容：** * **VHDL基础：** 重点讲解VHDL语言，特别是信号（signal）与变量（variable）对象的区别与应用。课程会详细阐述变量对象立即更新，而信号对象更新延迟的特性，并通过Modelsim仿真深入剖析其行为。 * **逻辑电路设计：** 学习组合逻辑和时序逻辑电路的设计方法，并通过Modelsim仿真直观展示其工作原理。 * **仿真与综合工具：** 强调Modelsim用于仿真，Vivado用于电路综合和FPGA编程的优势。课程会解析“可仿真但不一定可综合”的概念，并结合Vivado平台给出实例说明。 * **FPGA实践：** 部分VHDL代码将实际加载到FPGA开发板上进行演示，帮助学员将理论知识应用于实践。 **学习方式：** 课程提供大量视频讲解，内容涵盖VHDL语言在电路设计中的运用，以及Modelsim和Vivado平台的使用技巧。
In this course, we will teach VHDL circuit design. The fundamental concepts about VHDL circuit design will be provided. In addition, practical examples using FPGA development boards will be provided. Combinational and clocked logic circuit design will be explained by examples. We will use either VIVADO or MODELSIM platform for the simulation and development of VHDL designs. Some of the written codes will be loaded into FPGA cards for demonstration purposes.We use MODELSIM for simulation of the VHDL codes. In VHDL circuit design, good knowledge of signal and variable objects is necessary, and the engineer should know the differences between signal and variable objects very well. The most confusing part between the signal and variable objects is that variable objects are updated immediately whereas update of the signal objects is not immediate. Clock division operation and behavior of the signal and variable objects are explained in details using MODELSIM simulations. The behaviors of the combinational and sequential circuits are clarified using MODELSIM simulations.We use VIVADO platform for simulation and circuit synthesis of the VHDL codes. In fact, it is better to use the MODELSIM platform for simulations and VIVADO platform for circuit synthesis and FPGA programming. We indicate that a VHDL code which can be simulated may not be synthesizable, and we explain this concept providing examples on VIVADO platform. Through the course, we provide many videos explaining VHDL language for circuit design and use of MODELSIM and VIVADO platforms for simulation and circuit synthesis.
