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所在平台: Udemy |
课程主页: https://www.udemy.com/course/synthesis-and-static-timing-analysissta-demo-with-tools/
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课程名称：Synthesis-STA-Physical Design(PD):Cadence+Synopsys Tool flow 课程概述： 本课程针对所有希望学习ASIC综合和静态时序分析（STA）的学生，适合不同程度的学习者，包括有志于进入VLSI领域的电子工程学生和希望获得实习机会的工程师。课程主要分为三个部分，具体内容如下： 第一部分：综合与静态时序分析（STA） 1. 简要介绍ASIC流程 2. 逻辑综合第一部分 - 综合的输入和输出、综合约束、库文件 3. 逻辑综合第二部分 - 使用Cadence Genus工具流的综合演示 4. 物理综合 - 各种文件格式及其描述、门的物理尺寸 5. 时序概念 - 设置时间、保持时间、延迟、时序预算等 6. 静态时序分析 7. 时序路径 - 从时钟到输出的延迟、输入和输出延迟等，使用Cadence Tempus工具流进行STA 8. 时序约束及多种模式 - MMMC 9. 时序例外 - 虚假路径、多周期路径 10. 综合和STA作业 - APB定时器 第二部分：使用Cadence工具的物理设计流程 - APB UART设计 11. 物理设计的输入 12. Innovus工具步骤 13. 平面布局 14. 平面布局演示 15. 放置 16. CTS（时钟树综合） 17. CTS演示 18. 路由 19. SDC_MMMC_PVT角 20. 物理验证 21. 使用Cadence Innovus工具流的物理设计作业 - APB定时器设计 第三部分：使用Synopsys工具的物理设计流程 - RISCV处理器设计 22. DC综合 23. ICC2流程介绍 24. ICC2初始化 25. ICC2平面布局 26. ICC2电源规划 27. ICC2放置 28. ICC2 CTS 29. ICC2路由与芯片后期处理 30. Formality - 逻辑等效检查（LEC） 31. PrimeTime - 布局后STA 32. 使用Synopsys工具的综合和物理设计作业 所有话题均详细讲解，并配有示例和图示。每个部分都设置了作业，便于实践操作。课程由具有丰富项目经验和实际操作的VLSI行业从业者授课。为获得最佳学习效果，建议使用相关工具进行实践（这些工具可能在你的院校或公司可用）。 祝学习愉快！
Section 1: Synthesis and Static Timing Analysis (STA) This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA. Electronics students, who want to internships, Engineers who want to start career in VLSI field. The course covers the following chapters: 1. ASIC flow in brief2. Logical synthesis Part 1 - inputs and outputs of synthesis, synthesis constraints, Libraries3. Logic Synthesis Part II - Synthesis demo using Cadence Genus tool flow4. Physical Synthesis - Various file formats and descriptions, Physical dimensions of gates5. Timing concepts - Setup time, hold time, slack. violations, timing budgets6. Static Timing Analysis - 7. Timing paths - Clock to output, propagation delay, input delay, output delay etc, STA using Cadence Tempus tool flow8. Timing constraints and various modes - MMMC9. Timing Exceptions - False path, multi cycle path10. Synthesis and STA assignment - APB TimerSection 2: Physical Design Flow using Cadence Tools - APB UART Design11. Inputs to Physical Design12. Innovus Tool Steps13. Floorplan14. Floorplan demo 15. Placement 16. CTS17. CTS Demo18. Routing19. SDC_MMMC_PVT Corners20. Physical Verification21. Physical design assignment using cadence innovus flow - APB Timer design Section 3: Physical Design Flow using Synopsys Tools - RISCV Processor Design22 DC Synthesis23. ICC2 Flow Introduction 24. ICC2 Initialization25. ICC2 Floorplan26. ICC2 PowerPlan27. ICC2 Placement28. ICC2 CTS29. ICC2 Routing & Chip Finishing30. Formality - Logic Equivalence Check (LEC)31. PrimeTime - Post Layout STA32. Synthesis and Physical Design Assignment using Synopsys tools - This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA. Electronics students, who want to internships, Engineers who want to start career in VLSI field. The course covers the following chapters: All the topics are elaborated with detailed examples, illustrated with diagrams, where required. Clear explanation; assignments added at the end of the course for practicing hands on examples. The lecture is given by hands on practitioners from the VLSI industry, who have worked on multiple projects and taped out chipsFor best take away from the course, kindly do hands on using tools (may be available in your institutions/companies). All the best - Happy learning
