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所在平台: Udemy |
课程主页: https://www.udemy.com/course/static-timing-analysis-vlsi/
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**课程名称：VLSI静态时序分析 (Static Timing Analysis: VLSI)** **课程概述：** 本课程是成为芯片设计工程师的必备课程，旨在帮助您设计出满足所有时序约束的数字电路。我们将深入探讨VLSI静态时序分析的核心概念和技术，让您能够理解并解决实际设计中的时序问题。 **主要学习内容：** 1. **数字电路类型：** 组合逻辑电路与时序逻辑电路。 2. **存储单元工作原理：** 锁存器 (Latches) 和触发器 (Flip-flops)。 3. **边沿触发 (Edge Triggering)：** 理解触发器的工作方式。 4. **组合逻辑电路中的延迟：** 传播延迟 (Propagation delay) 和 时钟传播延迟 (Contamination delay)。 5. **组合逻辑电路的关键路径 (Critical path)：** 识别影响电路性能的最长延迟路径。 6. **时序电路的时序规范 (Timing specifications)：** 了解时序约束的组成。 7. **启动触发器 (Launch Flipflop) 与捕获触发器 (Capture Flipflop)：** 理解数据在时序电路中的流动路径。 8. **建立时间分析与违例 (Setup time analysis & violation)：** 确保数据在时钟上升沿到来前稳定。 9. **保持时间分析与违例 (Hold time analysis & violation)：** 确保数据在时钟上升沿过后保持稳定。 10. **时序电路中的不同时序路径：** 全面分析所有可能的数据传输路径。 11. **计算最大延迟 (关键路径延迟)：** 确定电路的性能瓶颈。 12. **计算最小和最大时钟周期/工作频率：** 确定电路的可行工作频率范围。 13. **数据要求时间 (Data Required Time) 与数据到达时间 (Data Arrival Time)：** 分析数据在设计中的时间窗口。 14. **时序裕量 (Slack) 分析：** 建立时间裕量 (Setup Slack) 和 保持时间裕量 (Hold Slack)。 15. **时钟偏斜 (Clock skew) 概念及其方程：** 理解时钟信号到达不同触发器的时间差异。 16. **时钟偏斜对最大频率的影响：** 分析时钟偏斜对电路性能的影响。 **附加内容：** 课程最后将通过解决示例问题和面试题，巩固所学概念和方程，帮助您应对实际挑战。 **课程重点：** 本课程将详细分析电路中的每一个触发器到触发器路径，重点研究目标触发器的数据建立时间以及路径上的传播延迟。在确定了电路的最大时钟频率后，我们将检查每个触发器到触发器的路径是否满足触发器保持时间的要求。如果沿此路径的最小延迟（时钟传播延迟）大于或等于目标触发器的最小建立时间，那么电路即可按预期运行。
Want to become a chip design engineer? Then, STA is mandatory for you!Welcome to my course on 'Static Timing Analysis on VLSI Circuits'This course will help you to design a digital circuit meeting all the timing constraints given. The contents that we will be discussing in this course are1. Types of digital circuits - Combinational, Sequential2. Working of Memory Elements - Latches, Flipflops3. Edge Triggering4. Different delays in a combinational circuit - Propagation delay, Contamination delay5. Critical path of a combinational circuit6. Timing specifications of a sequential circuit7. Launch Flipflop, Capture Flipflop8. Setup time analysis & violation9. Hold time analysis & violation10. Different timing paths in a sequential circuit11. Finding out the maximum delay (critical path delay)12. Minimum clock period, Maximum operating frequency of the circuit13. Data Required Time, Data Arrival Time14. Slacks - Setup Slack, Hold Slack.15. The concept of clock skew and its equation16. Effect of clock skew on the maximum frequency of the circuit.After understanding the concepts and the equations, Some example problems and interview questions will be solved in the last section. A clock signal is used by sequential circuits to regulate the flow of system data. The maximum clock frequency that can be employed in the circuit can be calculated from a set of combinational and sequential components and the timing parameters that go with them. In this study, each flip-flop to flip-flop path in the circuit is looked at. Both the data setup time at the destination flip-flop and the propagation delays throughout the pathways are examined. Each flip-flop to flip-flop path can be checked to see if flip-flop hold times are satisfied after figuring out the maximum clock frequency. The circuit will function as intended if the contamination delays along each path are more than or equal to the target flip flop hold time.
