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所在平台: Udemy |
课程主页: https://www.udemy.com/course/simple-axi-bus-design-using-verilog-hdl/
课程评论：没有评论
**课程名称：** 使用 Verilog HDL 设计简单的 AXI 总线 **课程概述：** 本课程深入探讨了 Arm 公司开发的开放标准 SoC (System on Chip) 设计规范 AMBA (Advanced Microcontroller Bus Architecture)，特别是其核心协议 AXI (Advanced Extensible Interface)。 AMBA 旨在实现高性能、模块化和可复用的 AND FIRST TIME (T.F.T.) 设计，同时最大限度地降低功耗和硅面积。AXI 协议最初是为了满足高频集成电路的设计需求而生，它提供的接口能够灵活地连接各种组件，适用于高频率、低延迟的设计场景。AXI 协议在保持向后兼容 AHB (Advanced High-performance Bus) 和 APB (Advanced Peripheral Bus) 的基础上，引入了多项新特性。 课程还将回顾 AHB 总线的工作原理，包括其单通道架构、优先级仲裁机制、中央译码器以及分块传输（包含地址/控制阶段和数据阶段）。 与 AHB 类似，AXI 协议也支持分块传输，并包含相似的地址和控制阶段。然而，AXI 的主要优势在于其多通道设计，使用独立的通道进行读写操作，这大大提高了效率。此外，AXI 还新增了诸如乱序事务处理、非对齐数据传输、缓存支持信号以及低功耗接口等先进功能。 **学习价值：** 通过学习 AXI 协议，您将能够深入理解 SoC 的内部工作原理，提升作为一名设计师的全面性和灵活性。 **参考资料：** AMBA AXI Protocol v1.0
AMBA is an open standard for SoC design created by Arm to allow for high-performance, modular, and reusable designs that work right the first time while minimizing both power and silicon. This course discusses the AMBA, which introduced the Advanced Extensible Interface (AXI) protocol.Originally conceived for high-frequency systems, the AXI protocol was designed to meet the interface requirements for a wide range of components, while allowing for flexibility in how those components are interconnected. Suitable for high-frequency, low-latency designs, AXI remains backward compatible with the AHB and APB from the previous AMBA revision.Understanding AXI will give you deep insight into how an SoC works while making you a versatile and well-rounded designer. Recall that the AHB (Advanced High-Performance Bus) is a single-channel bus that multiple masters and slaves use to exchange information. A priority arbiter determines which master currently gets to use the bus, while a central decoder performs slave selection. Operations are performed in bursts that can take multiple bus cycles to complete. Every burst transfer consists of an address and control phase followed by a data phase. AXI was designed with a similar philosophy but uses multiple, dedicated channels for reading and writing. AXI is burst-based like its predecessor and uses a similar address and control phase before data exchange. AXI also includes several new features including out-of-order transactions, unaligned data transfers, cache support signals, and a low-power interface. You can refer to AMBA AXI Protocol v1.0 for a deeper look into the AXI.
