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所在平台: Udemy |
课程主页: https://www.udemy.com/course/online-verilog-hdl-mastery/
课程评论：没有评论
课程名称：在线Verilog HDL精通课程 课程概述：本课程旨在帮助初学者和中级学习者深入理解Verilog HDL。Verilog是一种描述数字系统（如微处理器、存储器和触发器）的重要语言，能够用来建模任何电子元件并生成相应的原理图。本课程结构严谨、内容简明，适合零基础及有经验的学习者，通过实例学习使内容更易于理解。每个设计都配有测试平台，帮助学生掌握验证和测试的方法。此外，课程还介绍了VLSI设计流程以及不同的Verilog HDL建模方式，包括门级模型、数据流模型、行为模型、结构模型和开关级模型，并通过实例进行讲解。 具体内容包括： - 使用门级模型讲解的半加器、全加器和解码器的Verilog代码。 - 数据流模型下的4:1多路复用器Verilog代码。 - 行为模型概念以及编码器的Verilog代码编写和测试平台说明。 - 循环语句及相关实例的详细讲解。 - 使用NAND门、CMOS反转器和多路复用器的结构模型与开关级模型示例。 - 有关梅雷机和摩尔机的ASM图概念。 - 以及针对PAL、PLA和PROM的可编程逻辑器件（PLDs）问题解决方案。 完成本课程后，学员将能够自信地编写带测试平台的Verilog代码，并能够为有限状态机（FSM）模型建立ASM图。
To describe any digital sysytem -microprocessor,memory,flip flop,verilog is used.using verilog we can model any electronic component and generate the schematic for the same.A beginer or an intermediate eager to grasp and understand verilog HDL.This course if for youonline verilog HDL course with perfect and well structured and concise course for freshers and experienced,as it is from scratch level. Learning through examples makes them very simpler to learn.Test bench for each design and knowing how to test and validate them.This course gives information related to VLSI design flow.This course gives information on different modeling on verilog HDL code i.e Gate level model,data flow model,behavioural model,structural model,switch level model with examples.verilog code with test bench on half adder,full adder,decoder using gate level is explained.verilog code for 4:1 mux using data flow model is explained.concept of Behavioral model with encoder verilog code writing with test bench is explained.looping statement with examples is clearly explained.structural model with examples.switch level model with example using NAND gate,cmos invertor,multiplexer.ASM chart concept for melay and moore machine.Plds concept with solving problems on PAL,PLA,PROM.After completing this course ,you can confidently write verilog code with test bench.you can built ASM chart for FSM model.
