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所在平台: Udemy |
课程主页: https://www.udemy.com/course/learning-uvm-testbench-with-xilinx-vivado-2020-for-newbie/
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《使用Xilinx Vivado 2020学习UVM验证平台》Coursera课程内容总结： 本课程是基于UVM（Universal Verification Methodology）的实践型课程，旨在教授学员如何使用SystemVerilog和UVM来构建高效的RTL验证平台。随着系统复杂性的不断提高，SystemVerilog凭借其强大的功能和可重用性成为验证领域的首选语言，而UVM则提供了一个标准化的、结构化的验证框架，极大地提高了验证效率。 课程将详细介绍UVM的核心概念和组件，包括： * **事务（Transaction）**：定义待测设计的输入和输出数据。 * **生成器（Generator）**：创建和生成测试事务。 * **序列器（Sequencer）**：负责管理和排序事务序列。 * **驱动器（Driver）**：将事务转换为 DUT（Design Under Test）能够理解的激励。 * **监视器（Monitor）**：捕获 DUT 的输入和输出信号，并将其转换为事务。 * **记分卡（Scoreboard）**：接收监视器产生的事务，并与期望结果进行比较，判断测试通过与否。 * **代理（Agent）**：将驱动器、监视器和序列器等组件进行封装，实现对接口的收发。 * **环境（Environment）**：集成代理、配置数据库等，构建完整的验证环境。 * **测试（Test）**：定义具体的激励序列和配置，驱动整个验证流程。 课程强调**配置数据库（configuration database）**的重要性，它能够灵活地进行验证环境的配置和参数传递，这在过去的验证语言中是难以实现的。 本课程特别适合**初学者**，即使没有面向对象编程（OOPS）或SystemVerilog的先验知识，也可以通过课程中的**大量编码练习、项目和简单示例**，逐步掌握UVM组件的编写，从而建立扎实的UVM基础。 学习本课程将使VLSI领域的学生和从业者能够快速掌握UVM这一行业事实标准，为他们在验证领域开辟职业道路奠定坚实的基础。UVM在验证领域有着长远的发展前景，学习UVM将为您的职业生涯提供强大的竞争力。
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the Verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.The course will discuss the fundamentals of the Universal Verification Methodology. This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test. Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM.
