System Verilog (SV) Language + Project Demo

所在平台: Udemy

课程主页: https://www.udemy.com/course/ip-verification-using-system-verilog-part-i/

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课程名称:System Verilog (SV) 语言 + 项目演示 课程概述:本课程旨在为初学者到专家提供系统的 System Verilog 学习内容,课程模块设计使学员能够在几周内学习和实践。课程内容分为两个部分。 第一部分: - **第一节** - ASIC 流程 - 设计验证和 Verilog 回顾 - 实验 1 - Verilog 测试平台开发 - **第二节** - System Verilog 介绍、数据类型 - 实验 2 - 使用各种数据类型编写程序 - **第三节** - 运算符、控制语句和循环 - 实验 3 - SV 结构实践 - **第四节** - 数组、队列 - 实验 4 - 数组、队列结构实践 - **第五节** - 面向对象编程(OOP)- 类和对象 第二部分: - **第六节** - 随机化和约束 - 实验 6 - 随机化 - **第七节** - 进程间通信 - 实验 7 - 使用邮箱、信号量和队列 - **第八节** - 接口 - 实验 8 - 使用接口、模块端口和时钟块 - **第九节** - 测试平台开发 - 实验 9 - 使用 SV 结构开发驱动程序/BFM - **第十节** - 代码和功能覆盖 - 实验 10 - 模拟一个覆盖示例 课程中详细解释了各种示例代码,其中一些程序在工业标准仿真器中得到模拟。此外,课程还针对一个协议示例开发了测试平台代码,并为项目编写了测试用例。课程作业旨在帮助学员练习代码编写,并进一步用于测试平台和测试用例的开发。

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课程详情

System Verilog course content is designed for beginners to experts ; The modules can be learnt and practiced in couple of weeks: The detailed course syllabus is as follows: It is split into 2 partsSection I:Session 01 • ASIC flow-Design verification and Verilog Refresh Lab 1 - Verilog Testbench developmentSession 02 •System Verilog Introduction, Data Types Lab 2 - Programs with Various data typesSession 03 •Operators-Control Statements-loopsLab 3- SV Constructs practiceSession 04 •Arrays, QueuesLab 4 - Arrays, Queues Constructs practiceSession 05 •OOPs-Classes-Objects Section II:Session 06 •Randomization and ConstraintsLab 6- RandomizationSession 07 •Inter process CommunicationLab 7- Use of mail box, Semaphores and QueuesSession 08 •Interfaces Lab 8-Use of interfaces, mod port, clocking blockSession 09 • Testbench developmentLab 09- Use of SV constructs for driver/BFMSession 10 •Code and Functional Coverage Lab 10-Simulate an example for coverageVarious example codes are explained in the course. Few of the programs are simulated in the industry standard simulators.A protocol example is also taken and testbench code is developed and test cases are written for the project.The assignment given helps to practice the code writing and further using for test bench and testcase development

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