Introduction to VHDL for FPGA and ASIC design

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课程主页: https://www.udemy.com/course/introduction-to-vhdl-for-fpga-and-asic-design/

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课程简介

**课程名称:** VHDL入门:FPGA和ASIC设计 **课程概述:** 本课程共十二讲,从VHDL基础知识讲起,包括实体(entity)、架构(architecture)和进程(process)。课程将详细讲解顺序VHDL(sequential VHDL)和并发VHDL(concurrent VHDL)的区别,并探讨良好的同步设计方法。此外,课程还将演示如何使用Altera Modelsim和Xilinx Vivado仿真器。为提供实践经验,本课程包含六个实验项目,讲师将展示其完成实验的方法。

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课程详情

Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process. Explanations of the difference in sequential and concurrent VHDL. Discussions of good synchronous design methodology. Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.

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