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所在平台: Udemy |
课程主页: https://www.udemy.com/course/icfpga-design-p2-verilog-for-design-and-verification/
课程评论：没有评论
课程名称：VLSI/FPGA 设计 P2：Verilog 设计与验证 概述：本课程将通过示例和编码练习，帮助学习者快速掌握 VLSI/FPGA 设计中的 Verilog 语言，视频时长不到 10 小时。学习完成后，您将能够将电路原理图、Verilog 代码和波形之间进行一致性匹配，可以根据其中任意一个推导出其他两个。本章节分为多个免费部分，将会讲解以下内容： 1. 数字 IP/IC 设计流程； 2. 数字基础知识的快速回顾； 3. 安装 Verilator 和 GTKwave； 4. 设计与验证中常用的 Verilog 语法； 5. 组合逻辑设计（基本门电路、MUX、解码器、一热解码器）； 6. 顺序逻辑设计（同步 DFF、异步 DFF）； 7. 设计小而实用的模块（计数器、边缘检测、移位寄存器、序列检查、同步 FIFO）； 8. 设计有限状态机（FSM）； 9. 设计基本测试平台； 10. 合成中常见错误（不完整的敏感列表、锁存器、多驱动、组合逻辑循环）； 11. 实践时间：设计并验证 z-scan 和复杂序列检查（FSM）。 本章节是整个数字 IC 和 FPGA 设计课程的第二部分第一节。在整个课程中，我将介绍数字 IC 和 FPGA 设计的基本原理，包含 12 个以上的编码练习和 3 个课程项目。理论部分包括：MOS 晶体管 -> 逻辑单元 -> 算术数据通路 -> Verilog 语言 -> 常用硬件功能模块和架构 -> 静态时序分析 (STA) -> 片上总线 (APB/AHB-Lite/AXI4) -> 低功耗设计 -> 可测试设计 (DFT) -> 系统级芯片 (SOC，MCU 级别)。 功能模块和架构包括：FSM、流水线、仲裁器、时钟域交叉 (CDC)、同步 FIFO、异步 FIFO、乒乓缓冲、带控制的流水线、滑窗、流水线冒险与转发路径、阵列式计算等。项目内容包括：简单接口的 SHA-256 算法、APB/AXI 接口的 SHA-256、APB/AXI 接口的 2D DMA 控制器。 在解释每个硬件架构后，我会提供一个编码练习，附带参考代码。编码难度从几行到五十行，再到一百多行，最后大项目将达到一千多行。希望这些知识和技能是您进入这个领域所必需掌握的。 我会尽力向您解释“什么”、“如何”和“为什么”，并鼓励您在这门课程中做得更好。请访问我在 Udemy 的主页以获取本课程每个章节的信息。
The speech isn't fluent, please turn on subtitle to help your understanding.If you don't need Q & A, you can also find a free version of this chapter at my homepage of Udemy.Quick master through examples and coding exercises, in videos less than 10 hours. After study, you can have the ability of consistency between circuit schematic, Verilog code and waveform. That's given anyone of them, you can figure out the other two. In this chapter (will be divided to several free sections), I'll explain:1: Digital IP/IC design flow;2: Quick review of digital fundamental3: Install Verilator and GTKwave4: Common used Verilog syntax for design and verification5: Design combination logic(basic gates, MUX, decoder, one-hot decoder)6: Design sequential logic(sync-DFF, async-DFF)7: Design small but useful block(counter, edge detect, shift registers, sequence check, sync_fifo)8: Design FSM(finite state machine)9: Design basic testbench10: Common mistakes for synthesis(incomplete sensitive list, latch, multi-driven, combination logic loop)11: Practice time: design and verify z-scan and complex sequence check(FSM)This is chapter 2, section 1 of whole Digital IC and FPGA design course.In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.I suppose these should be essential knowledge and skills you need master to enter this area.I will try my best to explain what-> how-> why and encourage you to do it better in this course.Please browse to my homepage on Udemy to obtain information about each chapter of this course.
