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所在平台: Udemy |
课程主页: https://www.udemy.com/course/high-level-synthesis-for-fpga-part-3-advanced/
课程评论：没有评论
Coursera 课程摘要：FPGA 高层次综合（HLS）- 高级篇 本课程是关于 FPGA 高层次综合（HLS）设计流程的进阶主题。本课程的目标是教授学员仅使用 C/C++ 语言，无需任何硬件描述语言（如 VHDL 或 Verilog），即可描述、调试和实现 FPGA 上的逻辑电路。HLS 已被 Nvidia 和 Google 等行业领导者广泛应用于其软硬件平台设计，是未来硬件设计的趋势，也是每一个希望利用 FPGA 的卓越性能和低功耗的硬件或软件工程师必备的技能。 作为 HLS 设计流程的高级专题的第一门课程，本课程将使用 Xilinx HLS 软件和硬件平台，通过真实的示例和应用来演示。课程中将包含大量 HLS 概念和技术的示例，以及丰富的测验和练习，帮助学员掌握所提出的方法和技术。 此课程是 HLS 系列课程的第三部分，重点在于设计硬件模块和加速 FPGA 上的算法。在前几门系列课程中，学员将学习如何使用单周期设计技术来开发 HLS 中的组合逻辑和时序逻辑电路。而本课程则专注于多周期设计、高级设计和优化技术。
This course covers advanced topics in high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design. It quickly becomes a must-have skill for every hardware or software engineer keen on utilising FPGAs for their exceptional performance and low power consumption.This course is the first to explain the advanced HLS design flow topics. It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises to practice and master the proposed methods and approaches.This course is the third of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on multi-cycle design, advanced design, and optimisation techniques in HLS, the other courses in the series explain how to use single-cycle design techniques to develop combinational and sequential logic circuits in HLS.
