|
所在平台: Udemy |
课程主页: https://www.udemy.com/course/high-level-synthesis-for-fpga-part-2-sequential-circuits/
课程评论：没有评论
课程名称：高层次综合（HLS）针对FPGA的设计，第二部分 - 顺序电路 课程概述：本课程是高层次综合（HLS）中顺序电路设计的入门介绍。课程的目标是利用C/C++语言描述、调试和实现FPGA上的顺序逻辑电路，而无需依赖硬件描述语言（HDLs），如VHDL或Verilog。课程将使用Xilinx HLS软件和硬件平台，展示真实的示例和应用。主要使用Xilinx Vitis-HLS工具集，将高层次设计描述转换为等效的HDL代码，并介绍如何在Vivado中使用集成逻辑分析仪（ILA）IP，对Basys3开发板进行实时调试。 本课程是首个从零开始构建HLS设计流程和数字逻辑电路概念的课程。在课程中，您将通过多个示例深入理解HLS的概念和技术，课程包含大量的测验和练习，帮助您练习和掌握所提议的方法。此外，课程还利用三个精彩的项目，将所有解释的概念结合在一起，设计真实的电路和硬件控制器。 本课程是关于 HLS 设计硬件模块及加速算法在目标 FPGA 上系列课程的第二部分。此课程专注于顺序电路，而第一课程则讲解了如何在 HLS 中描述组合电路。系列中的其他课程将解释如何使用 HLS 进行高级逻辑电路的设计、算法加速和混合 CPU + FPGA 异构系统的设计。
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.
