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所在平台: Udemy |
课程主页: https://www.udemy.com/course/fundamentals-of-verification-and-system-verilog/
课程评论：没有评论
课程名称：验证与SystemVerilog基础 课程概述：本课程旨在为希望学习验证基本概念和SystemVerilog基本概念的学习者提供入门指导。本课程假设学习者已具备Verilog硬件描述语言的基础知识。课程中，学习者将了解验证的必要性及其定义。同时，将介绍SystemVerilog中的一种验证语言构造。课程将讨论分层测试平台及其各个组成部分。此外，学习者还将接触到SystemVerilog中的各种数据类型、过程控制语句和接口。通过多个实例讲解，学习者可以通过每个章节的测验和作业来监测自己的学习进度。 该课程的特点是互动性强，能够帮助学习者深入理解验证，通过实践巩固所学知识。
This course is introduced for learners who wants to learn fundamental concepts of Verification and basic concepts of SystemVerilog. It is assumed that learner is aware of the Verilog hardware description language. In this course, learners will be introduced to why verification is to be done and what is verification. One of the verification language SystemVerilog constructs will be introduced. Layered testbench and its various components will be discussed. Learner's will also be introduced to various data types, procedural control statements and interfaces in SystemVerilog. Course is being taught with various examples and learner can monitor self-progress by attempting quiz and assignment in each section.
