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所在平台: Udemy |
课程主页: https://www.udemy.com/course/functional-coverage-and-assertions-in-systemverilog/
课程评论：没有评论
课程名称：SystemVerilog中的功能覆盖和断言 课程概述：随着科技的进步和设计的复杂性，验证行业日益增长。验证工程师面临的挑战是如何有效地监控验证计划的进展，并宣告验证过程已完成。如果你想了解什么时候可以宣告验证完成，那么这个课程非常适合你。课程将从功能覆盖的定义开始，深入探讨各种覆盖方法。学员将学习如何在SystemVerilog中编写类以执行覆盖，以及如何调整测试平台以实现验证目标。 本课程为希望学习SystemVerilog中功能覆盖和断言的学习者设计。参与者需具备验证的基本概念和SystemVerilog的基本结构，建议先完成“验证基础与SystemVerilog”课程。如果你对断言及其语义和语法感兴趣，这也是你理想的课程。学员将接触到断言的概念及基于断言的验证（ABV）方法，使用SystemVerilog断言（SVA）。本课程通过多个示例进行讲解，学员可通过每个章节的测验自我监测进度。所有课程中讨论的示例均可在免费的EDA Playground模拟器上进行模拟。 综上所述，这是一个专为希望深入了解SystemVerilog中的功能覆盖和断言的学习者开设的课程。
Verification industry is growing day by day due to advancements in the technology and complexities of design. It has become very challenging for verification engineers to monitor the progress of verification plan and declare that verification is complete. If you are wondering when the verification is declared to be complete then you should join this course. Starting from what is coverage to various ways of doing coverages are covered in this course. In this course, students will learn how to write a class in SystemVerilog to carry out the coverage and how to divert test bench so that verification goal is achieved.This course is introduced for learners who wants to learn Functional Coverage and Assertions in SystemVerilog. It is assumed that learner is aware of the fundamentals of verification and basic constructs of SystemVerilog. Learners can take this course after completing the course on ‘Fundamentals of Verification and SystemVerilog'.If you are interested to learn about assertions and also briefly about various semantics and syntax used for assertions then this is the appropriate course for you. Learners will be introduced to concepts of assertions and 'Assertion Based Verification (ABV)' using 'SystemVeriog Assertions (SVA)'. Course is being taught with various examples and learner can monitor self-progress by attempting quiz in each section.All the example discussed in the course can be simulated using freely available simulator EDA Playground.This course is introduced for learners who wants to learn Functional Coverage and Assertions in SystemVerilog. It is assumed that learner is aware of the fundamentals of verification and basic constructs of SystemVerilog. In this course, students will learn how to write a class in SystemVerilog to carrry out the coverage, how to divert testbench so that verification goal is achieved etc. Learner's will also be introduced to concepts of assertions and 'Assertion Based Verification (ABV)' using 'SystemVeriog Assertions (SVA)'. Course is being taught with various examples and learner can monitor self-progress by attempting quiz in each section.
