|
所在平台: Udemy |
课程主页: https://www.udemy.com/course/fpga-design-with-high-level-synthesis-vivado-hls/
课程评论：没有评论
《使用Vivado HLS进行FPGA设计 - 高层综合》课程概述： 本课程是一门关于使用C/C++语言进行FPGA（现场可编程门阵列）设计的入门课程，重点介绍高层综合（HLS）技术。通过本课程，您将学习如何利用C/C++代码高效地生成FPGA硬件逻辑。 **课程内容涵盖：** * **HLS基础：** * 创建新的HLS项目。 * 运行C语言仿真，验证C/C++代码的正确性。 * 将C/C++源代码综合（转换）为Verilog/VHDL或SystemC等硬件描述语言。 * 运行C/RTL协同仿真，进一步验证综合后的硬件逻辑。 * 将HLS设计导出为IP（知识产权）核格式，以便在Vivado IP Integrator中使用。 * **计算机视觉应用：** * 从基础的HLS设计到实现复杂的计算机视觉应用。 * **实时Sobel边缘检测：** 学习如何设计Sobel边缘检测IP，将其导出到Vivado工具，并在Zybo FPGA上实现和测试。 * **Vitis HLS与OpenCV集成：** 课程还包含如何安装Vitis HLS，在Vitis HLS中设置OpenCV，并运行基于Vitis Vision 2020.2的示例。 * **实际项目实践：** * **C++语言实验：** 在C++中进行详细的实验，包括计数器、矩阵乘法器、频率调制器和数控振荡器（NCO）的设计、仿真、综合和实现（导出设计）。 * **Vivado IP Integrator集成：** 将导出的HLS项目与Zynq处理系统集成到Vivado IP Integrator中，并在Vivado IPI中进行综合和实现。 **学习目标：** 完成本课程后，您将能够独立完成HLS项目的**设计、仿真、综合、实现和导出**。您还将了解HLS如何利用丰富的C/C++库（如OpenCV）来简化计算机视觉、视频/图像处理以及复杂数学运算的FPGA实现，这些任务在传统的HDL/RTL实现中通常非常繁琐。
At the ending of this course, we also have included how to "install Vitis HLS, setup OpenCV in Vitis HLS and performing the Vitis Vision 2020.2 based examples".Learn from Basic HLS Design & C-Simulation to Design Computer Vision Application [Real Time Sobel Edge Detection]High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers: Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Exporting HLS Design in to IP core Format to VIVADO IP Integrator. We also have include session on "Sobel Edge IP design in HLS, exporting it to VIVADO tool and then implementing/testing it on Zybo FPGA". After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL. In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.
