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所在平台: Udemy |
课程主页: https://www.udemy.com/course/digital-timing-basics-for-vlsi-interview-physical-design/
课程评论：没有评论
课程名称：VLSI面试与SoC设计的数字时序基础 课程概述：本课程专为希望从事物理设计、前端（RTL）设计、验证和电路设计的VLSI学生与专业人士而设，是学习数字逻辑基本时序检查的重要基础。了解触发器、锁存器和逻辑门的时序（设置时间、保持时间、时钟到Q的延迟）对每位VLSI设计师至关重要。无论是物理设计师（后端）、RTL设计师（前端）、验证工程师还是电路设计师，数字逻辑及其相关时序都是SoC设计性能的基础。 时钟偏移是静态时序分析中的一个重要因素。本课程将涵盖触发器的关键时序方面，以及在数字设计中如何计算设置和保持裕度。此外，课程还将提供降低延迟的见解，这也是物理设计中的一个重要方面。对于希望在半导体行业获得成功职业的VLSI求职者来说，这是一门必修课程。如果您正在准备VLSI面试或GATE考试，这将是合适的学习选择。 本讲座系列中的所有概念都配有相关示例，帮助学生全面理解每个概念。课程由具有行业经验的VLSI专家准备，内容涵盖了来自德州仪器、AMD、英特尔、高通、Rambus和三星等公司的专业人士的意见。课程内容包括：触发器和锁存器的操作、设置时间、保持时间、时钟到Q的延迟、缓冲、时钟偏移、设置裕度、保持裕度、周期路径分析、数字与物理实现的比较、违反示例及修复、延迟最小化、时钟门控以及SoC中的频率-电压曲线。 祝您在VLSI学习旅程中一切顺利！
A VLSI Course on Basic Timing Checks for Digital Logics - A MUST Course for VLSI students and professionals intended to work in Physical Design / Front-end (RTL) Design / Verification / Circuit Design.Understanding of Flop, Latch and Logic Gates timings (Set-up time, hold-time, Clock to Q delay) is very crucial for every VLSI designer. Whether you are working as Physical Designer (back-end) or RTL designer (front-end) or Verification engineer or Circuit Designer, Digital logics and associated timings form the basis of design performance in SoC design.Clock skew is another important factor in Static Timing Analysis. This course will cover most critical timing aspects of Flops and how set-up and hold margins are computed in Digital design. In addition, this course will provide insights to latency minimization, another crucial aspect of Physical Design.This is a MUST Course for every VLSI aspirants who aspire for a successful career in semiconductor industry. If you are preparing for VLSI interview or GATE exam, then this is right course for you.All the concepts taught in this lecture series are followed by relevant examples which will help students to get a full understanding of each concept. This is perfect course for VLSI interview preparation.This Crash Course is prepared by VLSI industry expert with inputs from Industry professionals working in companies such as Texas Instruments, AMD, Intel, Qualcomm, Rambus, Samsung etc.Concepts covered in this course are - Flop and Latch operation, Set-up time, Hold time, Clock to Q delay, Buffer, Clock Skew, Set-up Margin, Hold Margin, Cycle path analysis, Digital vs Physical implementation, Example of violations and fixing those violations, Latency minimization, Clock-Gating and Frequency-Voltage Curve in SoC.All the best for your VLSI journey!
