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所在平台: Udemy |
课程主页: https://www.udemy.com/course/digital-icfpga-design-p4-sta-dc-synthesis/
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课程名称：VLSI/FPGA设计 P4: 静态时序分析与 DC 合成 课程概述：本课程将介绍数字电路的静态时序分析（STA）方法，并提供使用Synopsys的Design Compiler进行合成的实例。特别优惠价为$12.99 USD，详情请联系SKY（通过DM或电子邮件：siliconthink@126.com）。 详细内容： 1. STA原理 2. 标准单元库基础 3. 时钟在STA中的特性 4. 同时钟的设置/保持时序分析 5. 常用时序约束 6. 同一时钟域（同步路径）的时序分析 7. 不同钟域（异步路径）的时序分析 8. OCV概念 9. 使用Synopsys Design Compiler的合成实例（包括完整的TCL脚本） 本课程为全面数字IC与FPGA设计课程的第四章，课程将介绍数字IC和FPGA设计的基础知识，包含12个以上的编码练习和3个课程项目。理论部分内容包括：MOS晶体管、逻辑单元、算术数据路径、Verilog语言、常用硬件功能块和架构、STA、片内总线（APB/AHB-Lite/AXI4）、低功耗设计、DFT和系统级芯片（SOC，MCU级）。 功能块和架构包括：有限状态机（FSM）、流水线、仲裁器、时钟域交叉（CDC）、同步FIFO、异步FIFO、乒乓机制、控制流水线、滑窗、流水线冒险和前馈路径、超矩阵。项目包括：具有简单接口的SHA-256算法、带APB/AXI接口的SHA-256、带APB/AXI接口的2D DMA控制器。 每解释一个硬件架构后，将提供编码练习及参考代码，编码难度从数行到五十行，然百行，再到约二百行，最终大项目将超过1000行。课程旨在帮助学员掌握进入该领域所需的基本知识和技能。希望能够详细解释什么、如何以及为什么，并鼓励您在课程中不断进步。欢迎访问我在Udemy的主页获取课程各章节信息。
Please contact SKY (DM or E-mail to siliconthink@126.com) for special offer of $12.99 USD.In this chapter I will introduce how to do static timing analysis for digital circuit. And give you're a synthesis example using Design Compiler from Synopsys. Detailed contents:1: Principle of STA;2: Basics of stander cell library;3: Characters of clock in STA;4: Setup/hold timing analysis for same clock;5: Common used timing constraints;6: Timing analysis for same clock domain (synchronous path);7: Timing analysis for different clock domain (asynchronous path);8: Concept of OCV;9: Synthesis example using Design Compiler from Synopsys (including whole TCL script);This is chapter 4 of whole Digital IC and FPGA design course.In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.I suppose these should be essential knowledge and skills you need master to enter this area.I will try my best to explain what-> how-> why and encourage you to do it better in this course.Please browse to my homepage on Udemy to obtain information about each chapter of this course.
