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所在平台: Udemy |
课程主页: https://www.udemy.com/course/digital-icfpga-design-p3common-used-hardware-architectures/
课程评论：没有评论
课程名称：VLSI/FPGA设计P3：常用硬件架构 课程概述：本课程将介绍常用的硬件架构，内容包括：1. SRAM的行为及使用建议；2. 握手接口和同步FIFO；3. 最大时钟频率的管道技术；4. 仲裁器；5. 时钟域跨越（CDC）及异步FIFO；6. Ping-Pong架构；7. 带控制的管道；8. 带有风险和前向通路的管道；9. 滑动窗口。这些架构在处理复杂设计时非常有用，如RISC-V CPU核心、AI加速器等。为帮助学员掌握这些内容，每个章节将设置编程作业。 这是整个数字集成电路和FPGA设计课程的第三章，课程涵盖数字集成电路和FPGA设计的基础知识，共有12个以上的编程练习和3个课程项目。理论部分将包括：MOS晶体管、逻辑单元、算术数据路径、Verilog语言、常用硬件功能模块和架构、静态时序分析（STA）、芯片内总线（APB/AHB-Lite/AXI4）、低功耗设计、设计可测试性（DFT）和系统级芯片（SOC，微控制器级别）。 功能模块和架构将包括：有限状态机（FSM）、管道、仲裁器、CDC、同步FIFO、异步FIFO、Ping-Pong、带控制的管道、滑动窗口、管道风险和前向通路、以及流动阵列（systolic）。项目内容包括：带简单接口的SHA-256算法、带APB/AXI接口的SHA-256、带APB/AXI接口的2D DMA控制器。 在每个硬件架构的讲解后，将提供编程作业和参考代码。编程难度从几行代码到50行、100行，最终项目大约为1000行以上。我希望这些内容是进入这一领域所需掌握的基本知识与技能。我将努力解释“是什么”、“如何做”和“为何这样做”，并鼓励学员在课程中不断进步。请访问我的Udemy主页以获取本课程各章节的更多信息。
Please contact SKY (DM or E-mail to siliconthink@126.com) for special offer of $12.99 USD.In this chapter I will introduce common used hardware architectures, including:1: Behavior of SRAM and usage suggestions;2: Handshake interface and synchronous FIFO;3: Pipeline to maximal clock frequency;4: Arbiter;5: Cross clock domain (CDC) and asynchronous FIFO;6: Ping-Pong;7: Pipeline with control (feedback);8: Pipeline with hazard and forward path;9: Slide window;These are useful architectures engineer used to deal with complex designs, such as RISC-V CPU core, AI accelerator and so on. To help you mastering them, I will assign a coding exercise after each section.This is chapter 3 of whole Digital IC and FPGA design course.In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.I suppose these should be essential knowledge and skills you need master to enter this area.I will try my best to explain what-> how-> why and encourage you to do it better in this course.Please browse to my homepage on Udemy to obtain information about each chapter of this course.
