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所在平台: Udemy |
课程主页: https://www.udemy.com/course/digital-icfpga-design-p1-cmos-gates-arithmetic-datapath/
课程评论：没有评论
课程名称：VLSI/FPGA设计 P1：CMOS门与算术数据路径 课程概述：本课程是SOC和FPGA设计的基础，就如摩天大楼的砖块。第1章内容包括：1. CMOS门的行为特性：开关模型、过渡时间、延迟时间、PVT角。2. 利用CMOS门构建基本逻辑功能门：NAND、NOR、XOR、MUX。3. 使用基本逻辑门构建算术数据路径：加法器、减法器、乘法器和除法器，学习它们背后的硬件架构理念，并利用这些理念来优化设计。注册后，您可以通过Udemy的问答系统获得技术支持。此外，如果需要特别优惠，请联系SKY（通过DM或邮件至siliconthink@126.com）。 这门课程是整个数字IC和FPGA设计课程的第一章，内容涵盖数字IC和FPGA设计的基础知识，包括12+个编码练习和3个课程项目。理论部分涵盖MOS晶体管、逻辑单元、算术数据路径、Verilog语言、常用硬件功能模块和架构、静态时序分析（STA）、片上总线（APB/AHB-Lite/AXI4）、低功耗设计、测试可测试性（DFT）及SOC（单片机级别）。功能模块和架构内容包括FSM、管道、仲裁器、时序控制、同步FIFO、异步FIFO、乒乓FIFO、控制管道、滑动窗口、管道冒险和转发路径、脉动阵列等。项目内容包括带简单接口的SHA-256算法、带APB/AXI接口的SHA-256、带APB/AXI接口的2D DMA控制器。 在讲解每个硬件架构后，我将提供一个编码练习，并附上参考代码。编码难度从几行到五十行、超过一百行，再到大约二百行，而最终的大项目将超过1000行。我认为，这些知识和技能是您进入这一领域所需掌握的基础。我将尽力解释什么、如何、为什么，并鼓励您在课程中做到更好。请浏览我的Udemy主页，以获取有关本课程每一章的信息。
Please contact SKY (DM or E-mail to siliconthink@126.com) for special offer of $12.99 USD.This chapter is foundation of design SOC and FPGA, that's bricks of skyscrapers. Contents in chapter 1:1: Behavior and characteristics of CMOS gate: switch model, transition time, delay time, PVT corner.2: Using CMOS gate to build basic logic function gates: NAND, NOR, XOR, mUX.3: Build arithmetic datapth using basic logic gates: adder, subtractor, multiplier and divider. Learning the HW architecture ideas behind them, and use them to optimize your design.Once enrolled, you can get technic support through the Q & A system of Udemy.Let's cooperate and success.Note:This is chapter 1 of the whole Digital IC and FPGA design course.In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.I suppose these should be essential knowledge and skills you need master to enter this area.I will try my best to explain what-> how-> why and encourage you to do it better in this course.Please browse to my homepage on Udemy to obtain information about each chapter of this course.
