|
所在平台: Udemy |
课程主页: https://www.udemy.com/course/digital-design-using-verilog-hdl-programming-with-practical/
课程评论：没有评论
课程名称：完整的Verilog HDL编程（附示例与项目） 课程概述： 本课程提供了一个完备的Verilog HDL编程学习框架，适合初学者与有经验的工程师，内容覆盖从基础到应用的方方面面。课程详细讨论了Verilog HDL编程的概念，并与C语言进行了对比，阐述了其特点和优势。此外，课程还介绍了FPGA与ASIC的VLSI设计流程，并对两者进行了概述。 在课程中，学员将学习不同的编程风格，如门级、数据流、行为级以及开关级编程，辅以示例帮助理解。课程明确了验证的过程，包括仿真和编写测试平台，提供了如计数器、时钟分频器和脉冲发生器等实例。 本课程还讲解了如何使用测试平台编写验证模型，包括任务和系统任务，涵盖文件系统任务的实例，如向文件中写入数据、从文件中读取数据、将数据加载到内存以及随机数据生成器。课程将清晰展示有限状态机（FSM）的概念，包括如何绘制FSM、如何将其实现为硬件模型，以及如何将其转化为Verilog代码，适用于Mealy与Moore FSM的示例。 此外，课程还包括了一些项目，如内存控制器、FIFO控制器以及利用汉明码进行错误检测与纠错的项目，旨在提高学员的分析能力与项目处理能力。最后，课程为学员提供了有关FPGA的基本知识，介绍了如何将比特文件加载到FPGA中。
Complete Verilog HDL programming course with a perfect, well structured and concise course for freshers and experienced, as it is from fundamental level to the application level. This course discuss the concepts in Verilog HDL programming and properties compared with C-Language and discussing the features and advantages. In this course we give information related to VLSI design flow for FPGA & ASIC and gives overview about both.This course gives information on different styles of programming like Gate level, Data flow, Behavioral and switch level with examples. This course gives clear picture on verification, i.e. simulation and writing a test bench and some general examples like counter, clock diver using counter, pulse generator. This courses explains how to write verification models using test benches with task and system tasks with Examples. These examples includes, file based system tasks such as writing data in to file, reading data from file and loading data in to memory and random data generator. This courses shows clear picture on Finite State Machines (FSM) how to draw, how to realize it in to hardware model how ro translate in to verilog code for both Mealy & Moore FSM with examples. This course also shows some projects like Memory controller, FIFO controller and Error detection & correction using Hamming code, this improves ability to analyse and approach to Projects. Finally it gives basic knowledge on FPGA's like core concept how bit file is loaded in to FPGA.
