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所在平台: Udemy |
课程主页: https://www.udemy.com/course/digital-computer-logic-electronic-engineering-circuit-simulations/
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课程名称：完整的数字计算机工程电路仿真 课程概述：本课程为学习数字电子系统提供了坚实的基础，讲解数字计算机及类似机器中电子设备和子系统的工作原理。课程内容涵盖组合逻辑电路和时序逻辑电路，学习主题包括数制、布尔代数、逻辑系列、中规模集成(MSI)和大规模集成(LSI)电路、模拟到数字(AD)和数字到模拟(DA)转换等相关主题。完成课程后，学生将能够使用适当的技术和程序构建、分析、验证和故障排除数字电路，并测试相关设备。此外，本课程还演示了使用硬件描述语言(HDL)进行FPGA编程。学生将创建FPGA基本应用的项目，使用数字系统设计师所用的行业标准软件。该过程涉及多种组件，从确定项目背后的逻辑，到在部署前进行仿真，再到测试和查看结果，最终进行全面实施。 课程示例：以下是一个实现AND门的VHDL代码示例： ```vhdl library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity gate is port ( A: in std_logic_vector (0 to 9); B: in std_logic_vector (0 to 9); Y: out std_logic_vector (0 to 9) := (others => '0'); SEL: in std_logic_vector (3 downto 0); HEX_OUT: out std_logic_vector (0 to 6) ); end gate; ``` 这个课程为想要掌握数字电路设计与实现的学习者提供了全面的学习路径。
This course provides a solid foundation in digital electronic systems. How the electronic devices and subsystems work in a digital computer and similar machines. The course covers combination and sequential logic circuits. Topic study will include number systems, Boolean algebra, logic families, medium-scale integration (MSI) and large-scale integration (LSI) circuits, analog-to-digital (AD) and digital-to-analog (DA) conversion, and more related topics. Upon completion, students will be able to construct, analyze, verify, and troubleshoot digital circuits using appropriate techniques and procedures and test related equipment.This course also demonstrates the use of FPGA programming using HDL. Project creation of FPGA basic applications using industry-grade software used by digital system designers. This process involves a lot of components, from determining the logic behind the project to simulating before deployment to testing and seeing results before full implementation.Here is an example of VHDL programming: Here's your VHDL code implementing an AND gate using the requested format and labels: library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity gate is port ( A: in std_logic_vector (0 to 9); B: in std_logic_vector (0 to 9); Y: out std_logic_vector (0 to 9):= (others => '0'); SEL: in std_logic_vector (3 downto 0); HEX_OUT: out std_logic_vector (0 to 6) );end gate;
