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所在平台: Udemy |
课程主页: https://www.udemy.com/course/designing-riscv-cpu-in-verilog-and-fpga/
课程评论：没有评论
课程名称：使用Verilog设计RISC-V CPU及其FPGA实现 概述：本课程“使用Verilog设计RISC-V CPU及其FPGA实现”深入探讨定制处理器设计的精彩世界，重点关注开源的RISC-V指令集架构（ISA）。参与者将通过动手实践，学习如何用Verilog硬件描述语言（HDL）架构、描述和实现一个功能性RISC-V CPU核心，并将其部署在现场可编程门阵列（FPGA）上。 课程开始时将建立数字逻辑设计原则的坚实基础，回顾与复杂数字系统相关的重要Verilog构造。随后，将介绍RISC-V ISA（RV-32I），探讨其模块化、可扩展性及关键指令格式。学生将学习如何解析ISA规范并将其转化为硬件逻辑。 课程还将提供逐步的指南，帮助学生设置RISC-V工具链，包括汇编器和GCC编译器，以编写嵌入式C程序并将其编译为Hex代码，之后将其加载到FPGA以访问LED和UART等外设。 课程中的大部分内容将专注于单周期RISC-V CPU的逐步设计。涵盖的主题包括： - 指令取指单元：设计程序计数器和指令存储器接口。 - 解码单元：实现指令解码逻辑、寄存器文件访问和控制信号生成。 - 执行单元：构建算术逻辑单元（ALU）并处理数据路径操作。 - 存储单元：设计数据存储接口以完成加载和存储操作。 - 写回单元：更新寄存器文件中的计算结果。 - 控制单元：开发有限状态机（FSM）或组合逻辑，以协调CPU操作。 课程强调Verilog编码的最佳实践，包括模块化设计、参数化和健壮的测试平台创建。学生将学习如何使用行业标准工具模拟其Verilog设计，以在每个CPU开发阶段验证功能的正确性。 课程的后半部分集中于FPGA实现的实际方面。参与者将学习如何： - 将其Verilog CPU设计合成到门级网表。 - 进行布局与布线，将设计映射到特定的FPGA资源上。 - 生成用于编程FPGA的比特流。 - 在实际FPGA硬件上调试和测试其实现的CPU，通常通过集成LED和UART等外设实现基本输入输出和交互。 到课程结束时，学生不仅会对RISC-V架构和CPU设计原则有深入的理解，同时还将掌握将复杂数字设计从概念转化为FPGA上实际工作硬件实现的实践技能。这些知识在嵌入式系统、定制硅设计、硬件加速和计算机架构研究等职业生涯中具有重要价值。建议具有基本的数字逻辑和Verilog知识。 注意：本课程仅讨论和实现基础整数指令（RV32I），并需要一块FPGA板进行CPU的硬件实现，推荐使用Tang-9K等基础FPGA板即可。
This comprehensive course, "Designing RISC-V CPU in Verilog and its FPGA Implementation", offers a deep dive into the fascinating world of custom processor design, focusing on the open-source RISC-V instruction set architecture (ISA). Participants will gain hands-on experience in architecting, describing, and implementing a functional RISC-V CPU core using the Verilog Hardware Description Language (HDL) and deploying it on Field-Programmable Gate Arrays (FPGAs).The course begins by establishing a strong foundation in digital logic design principles and reviewing essential Verilog constructs relevant to complex digital systems. We will then introduce the RISC-V ISA (RV-32I), exploring its modularity, extensibility, and key instruction formats. Students will learn how to interpret the ISA specifications and translate them into hardware logic.This course also provides step-by-step guidelines to set up the RISC-V toolchain, including assembler and GCC compiler, to write an embedded-C programme and compile it to Hex code, which will be loaded into an FPGA to access peripherals such as LEDs and UART.A significant portion of the course is dedicated to the step-by-step design of a single-cycle RISC-V CPU. Topics covered will include:Instruction Fetch Unit: Designing the program counter and instruction memory interface.Decode Unit: Implementing instruction decoding logic, register file access, and control signal generation.Execute Unit: Building the Arithmetic Logic Unit (ALU) and handling data path operations.Memory Unit: Designing data memory interfaces for load and store operations.Write-back Unit: Updating the register file with computed results.Control Unit: Developing the finite state machine (FSM) or combinational logic to orchestrate CPU operations.Emphasis will be placed on best practices in Verilog coding for synthesis, including modular design, parameterization, and robust test bench creation. Students will learn how to simulate their Verilog designs using industry-standard tools to verify functional correctness at each stage of the CPU development.The latter part of the course focuses on the practical aspects of FPGA implementation. Participants will learn how to:Synthesize their Verilog CPU design into a gate-level netlist.Perform Place and Route to map the design onto specific FPGA resources.Generate bitstreams for programming the FPGA.Debug and test their implemented CPU on actual FPGA hardware, often by integrating peripherals like LEDs and UART for basic I/O and interaction.By the end of this course, students will not only have a thorough understanding of RISC-V architecture and CPU design principles but also possess the practical skills to bring a complex digital design from concept to a working hardware implementation on an FPGA. This knowledge is invaluable for careers in embedded systems, custom silicon design, hardware acceleration, and research in computer architecture. A basic understanding of digital logic and Verilog is recommended.Note: Only Base Integer Instruction (RV32I) is discussed and implemented in Verilog and FPGA. Also, you need one FPGA board for the hardware implementation of CPU. A basic FPGA board, such as Tang-9K, is sufficient for this.
