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所在平台: Udemy |
课程主页: https://www.udemy.com/course/design-verification-with-systemverilog-uvm/
课程评论：没有评论
**课程名称：** 使用 SystemVerilog/UVM 进行设计验证 **课程概述：** 本课程将带您深入学习 UVM 库的各项功能和精髓，并指导您如何从零开始构建一个强大的验证环境。通过循序渐进的教程，我们将逐步介绍 UVM 特性，并应用于完整的项目实践中。我们将利用 EDA Playground 平台进行开发，最终完成一个超过 5000 行代码的综合性项目，全面展示您的技能和知识。 **课程目标：** 通过本课程的学习，您将能够： * 熟练构建 UVM Agent 并理解其作用。 * 使用 UVM 库对设计寄存器进行建模。 * 在验证环境中设置待测设计（DUT）。 * 验证 DUT 的输出，确保其准确性和功能性。 * 在 SystemVerilog 中实现功能覆盖，以达到彻底的验证。 * 编写和执行随机测试，覆盖广泛的场景。 * 运用高级调试技术来识别和解决问题。 * 探索和利用 UVM 库的隐藏功能，以增强项目。 **学习成果：** 本课程所学技能将帮助您为入门级或初级验证工程师的面试做好准备，并确保您在新岗位上能够从第一天起就高效工作。
Master UVM Library & Create a Verification Environment: Comprehensive Course OverviewIn this course, you'll delve into two crucial areas:UVM Library: Uncover all its features, secrets, and how they can be applied effectively in verification environments.Verification Environment Creation: Learn the step-by-step process of building a robust verification environment from the ground up using UVM.Course Objectives:Throughout this course, we'll guide you through the development of a verification environment, meticulously designed using the UVM library. Each tutorial will introduce new functionalities, demonstrating the UVM features necessary for each phase of our comprehensive project.We'll leverage the EDA Playground platform to develop our verification environment. By the end of the course, our final project will encompass over 5000 lines of code, providing a substantial showcase of your acquired skills and knowledge.By the end of this course, you will master:Building UVM agents and understanding their rolesModeling design registers using the UVM librarySetting up a Device Under Test (DUT) within a verification environmentVerifying the outputs of a DUT to ensure accuracy and functionalityImplementing functional coverage in SystemVerilog to achieve thorough verificationWriting and executing random tests to cover a wide range of scenariosEmploying advanced debugging techniques to identify and resolve issuesExploring and utilizing hidden features of the UVM library to enhance your projectsThe skills you gain from this course will not only prepare you for entry or junior-level verification engineer job interviews but will also ensure you are productive and effective from day one in your new role.
