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所在平台: Udemy |
课程主页: https://www.udemy.com/course/custom-axi-interface-zynq-peripherals-for-newbie/
课程评论：没有评论
**课程名称：** **为Zynq设备构建自定义AXI接口外设** **课程概述：** 随着系统复杂性的日益增加，Zynq设备本身已难以满足高性能需求。因此，将纯RTL模块或可编程逻辑（PL）与Zynq集成变得至关重要。由于Zynq采用AXI（Advanced Extensible Peripheral）总线进行通信，FPGA工程师必须掌握如何为Verilog RTL添加AXI接口。AXI4提供了多种变体以适应不同的应用需求。理解AXI Lite和AXI Stream等较简单的变体，是进一步掌握AXI4（如AXI Full）等复杂变体的良好基础。 本课程重点介绍如何利用Vivado IP Integrator和Vivado RTL Integration方法，为纯Verilog模块构建自定义AXI接口。实现AXI接口添加到Verilog RTL主要有四种方式：使用Vivado IP Packager、Vivado RTL Integration、System Generator和Vivado HLS。本课程将详细讲解**Vivado IP Packager**和**Vivado RTL Integration**这两种方法，并通过简单示例演示如何创建IP以及将其集成到Zynq设备。此外，课程还将讨论创建基础设备驱动程序，展示如何编写软件来访问自定义外设的寄存器。
As system complexities are growing day by day, the Zynq device alone is incapable of providing the same performance and the Pure RTL module or Programmable logic (PL) needs to be integrated along with the Zynq. As Zynq works with Advanced Extensible Peripheral (AXI), it becomes mandatory for FPGA engineers to gain a fundamental understanding of adding AXI Interface to the Verilog RTL. The AXI4 offers different variants to fit diverse application needs. Understanding of the simpler variants such as AXI Lite and AXI Stream Interface lays a foundation for building an understanding of the complex AXI4 variant such as AXI Full. This course focuses on the usage of the Vivado IP Integrator and Vivado RTL integration for building the custom AXI interface for pure Verilog modules. There are four ways to achieve the addition of the AXI interface to the Verilog RTL viz. Using Vivado IP Packager, Vivado RTL Integration, Using System Generator, Using Vivado HLS. The course discusses two methodologies viz. Vivado IP Packager and Vivado RTL Integration in details with a simple example along with the demonstration of the integration of the created IP with the Zynq device. It will also discuss the creation of some basic device drivers, showing how software can be written to access the registers on the custom peripheral.
